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[Qemu-devel] [PULL 11/17] target/m68k: add reset
From: |
Laurent Vivier |
Subject: |
[Qemu-devel] [PULL 11/17] target/m68k: add reset |
Date: |
Thu, 4 Jan 2018 17:42:45 +0100 |
The instruction traps if the CPU is not in
Supervisor state but the helper is empty because
there is no easy way to reset all the peripherals
without resetting the CPU itself.
Signed-off-by: Laurent Vivier <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
---
target/m68k/helper.c | 7 +++++++
target/m68k/helper.h | 4 ++++
target/m68k/translate.c | 13 +++++++++++++
3 files changed, 24 insertions(+)
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
index af57ffcea9..52b054e1a3 100644
--- a/target/m68k/helper.c
+++ b/target/m68k/helper.c
@@ -711,3 +711,10 @@ void HELPER(set_mac_extu)(CPUM68KState *env, uint32_t val,
uint32_t acc)
res |= (uint64_t)(val & 0xffff0000) << 16;
env->macc[acc + 1] = res;
}
+
+#if defined(CONFIG_SOFTMMU)
+void HELPER(reset)(CPUM68KState *env)
+{
+ /* FIXME: reset all except CPU */
+}
+#endif
diff --git a/target/m68k/helper.h b/target/m68k/helper.h
index 78483da003..d27ea37d60 100644
--- a/target/m68k/helper.h
+++ b/target/m68k/helper.h
@@ -97,3 +97,7 @@ DEF_HELPER_FLAGS_4(bfffo_mem, TCG_CALL_NO_WG, i64, env, i32,
s32, i32)
DEF_HELPER_3(chk, void, env, s32, s32)
DEF_HELPER_4(chk2, void, env, s32, s32, s32)
+
+#if defined(CONFIG_SOFTMMU)
+DEF_HELPER_FLAGS_1(reset, TCG_CALL_NO_RWG, void, env)
+#endif
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index 98efe6b976..e8f7d07f3f 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -2762,6 +2762,18 @@ DISAS_INSN(unlk)
tcg_temp_free(src);
}
+#if defined(CONFIG_SOFTMMU)
+DISAS_INSN(reset)
+{
+ if (IS_USER(s)) {
+ gen_exception(s, s->insn_pc, EXCP_PRIVILEGE);
+ return;
+ }
+
+ gen_helper_reset(cpu_env);
+}
+#endif
+
DISAS_INSN(nop)
{
}
@@ -5572,6 +5584,7 @@ void register_m68k_insns (CPUM68KState *env)
#if defined(CONFIG_SOFTMMU)
INSN(move_to_usp, 4e60, fff8, USP);
INSN(move_from_usp, 4e68, fff8, USP);
+ INSN(reset, 4e70, ffff, M68000);
BASE(stop, 4e72, ffff);
BASE(rte, 4e73, ffff);
INSN(movec, 4e7b, ffff, CF_ISA_A);
--
2.14.3
- [Qemu-devel] [PULL 00/17] M68k for 2.12 patches, Laurent Vivier, 2018/01/04
- [Qemu-devel] [PULL 01/17] target-m68k: sync CC_OP before gen_jmp_tb(), Laurent Vivier, 2018/01/04
- [Qemu-devel] [PULL 03/17] linux-user, m68k: correctly manage SR in context, Laurent Vivier, 2018/01/04
- [Qemu-devel] [PULL 02/17] target/m68k: fix gen_get_ccr(), Laurent Vivier, 2018/01/04
- [Qemu-devel] [PULL 04/17] target/m68k: use insn_pc to generate instruction fault address, Laurent Vivier, 2018/01/04
- [Qemu-devel] [PULL 06/17] target/m68k: manage 680x0 stack frames, Laurent Vivier, 2018/01/04
- [Qemu-devel] [PULL 11/17] target/m68k: add reset,
Laurent Vivier <=
- [Qemu-devel] [PULL 08/17] target/m68k: add move16, Laurent Vivier, 2018/01/04
- [Qemu-devel] [PULL 13/17] target/m68k: move CCR/SR functions, Laurent Vivier, 2018/01/04
- [Qemu-devel] [PULL 05/17] target/m68k: add CPU_LOG_INT trace, Laurent Vivier, 2018/01/04
- [Qemu-devel] [PULL 14/17] target/m68k: add 680x0 "move to SR" instruction, Laurent Vivier, 2018/01/04
- [Qemu-devel] [PULL 16/17] target/m68k: add the Interrupt Stack Pointer, Laurent Vivier, 2018/01/04
- [Qemu-devel] [PULL 09/17] target/m68k: softmmu cleanup, Laurent Vivier, 2018/01/04
- [Qemu-devel] [PULL 07/17] target/m68k: add chk and chk2, Laurent Vivier, 2018/01/04
- [Qemu-devel] [PULL 17/17] target/m68k: fix m68k_cpu_dump_state(), Laurent Vivier, 2018/01/04
- [Qemu-devel] [PULL 10/17] target/m68k: add cpush/cinv, Laurent Vivier, 2018/01/04
- [Qemu-devel] [PULL 12/17] target/m68k: implement fsave/frestore, Laurent Vivier, 2018/01/04