Re: [Qemu-devel] [PATCH v1 21/21] RISC-V Build Infrastructure

[Antony Pavlov]

On Wed,  3 Jan 2018 13:44:25 +1300
Michael Clark <address@hidden> wrote:

> This adds RISC-V into the build system enabling the following targets:
> 
> - riscv32-softmmu
> - riscv64-softmmu
> - riscv32-linux-user
> - riscv64-linux-user
> 

...

> diff --git a/default-configs/riscv32-softmmu.mak 
> b/default-configs/riscv32-softmmu.mak
> new file mode 100644
> index 0000000..f9e7421
> --- /dev/null
> +++ b/default-configs/riscv32-softmmu.mak
> @@ -0,0 +1,4 @@
> +# Default configuration for riscv-softmmu
> +
> +CONFIG_SERIAL=y
> +CONFIG_VIRTIO=y
> diff --git a/default-configs/riscv64-linux-user.mak 
> b/default-configs/riscv64-linux-user.mak
> new file mode 100644
> index 0000000..865b362
> --- /dev/null
> +++ b/default-configs/riscv64-linux-user.mak
> @@ -0,0 +1 @@
> +# Default configuration for riscv-linux-user
> diff --git a/default-configs/riscv64-softmmu.mak 
> b/default-configs/riscv64-softmmu.mak
> new file mode 100644
> index 0000000..f9e7421
> --- /dev/null
> +++ b/default-configs/riscv64-softmmu.mak
> @@ -0,0 +1,4 @@
> +# Default configuration for riscv-softmmu
> +
> +CONFIG_SERIAL=y
> +CONFIG_VIRTIO=y
> diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
> new file mode 100644
> index 0000000..a0c31ae
> --- /dev/null
> +++ b/hw/riscv/Makefile.objs
> @@ -0,0 +1,12 @@
> +obj-y += riscv_elf.o
> +obj-y += riscv_htif.o
> +obj-y += riscv_hart.o
> +obj-y += sifive_e300.o
> +obj-y += sifive_clint.o
> +obj-y += sifive_prci.o
> +obj-y += sifive_plic.o
> +obj-y += sifive_u500.o
> +obj-y += sifive_uart.o
> +obj-y += spike_v1_09.o
> +obj-y += spike_v1_10.o
> +obj-y += virt.o

According to https://www.sifive.com/products/freedom/
Freedom E300 Platform uses RV32IMAC Architecture
and Freedom U500 Platform uses RV64GC Architecture.

Which means that qemu-system-riscv32 has to have E300 support but not U500 
support.
qemu-system-riscv64 has to have U500 support but not E300 support.

However please see this log:

riscv-qemu$ ./riscv32-softmmu/qemu-system-riscv32 -M ?
Supported machines are:
none                 empty machine
sifive_e300          RISC-V Board compatible with SiFive E300 SDK
sifive_u500          RISC-V Board compatible with SiFive U500 SDK <<<<<< U500 
in 32-bit mode
spike_v1.10          RISC-V Spike Board (Privileged ISA v1.10)
spike_v1.9           RISC-V Spike Board (Privileged ISA v1.9.1) (default)
virt                 RISC-V VirtIO Board (Privileged spec v1.10)
riscv-qemu$ ./riscv64-softmmu/qemu-system-riscv64 -M ?
Supported machines are:
none                 empty machine
sifive_e300          RISC-V Board compatible with SiFive E300 SDK <<<<<< E300 
in 64-bit mode
sifive_u500          RISC-V Board compatible with SiFive U500 SDK
spike_v1.10          RISC-V Spike Board (Privileged ISA v1.10)
spike_v1.9           RISC-V Spike Board (Privileged ISA v1.9.1) (default)
virt                 RISC-V VirtIO Board (Privileged spec v1.10)

I propose at least this fixup:

diff --git a/default-configs/riscv32-softmmu.mak 
b/default-configs/riscv32-softmmu.mak
index f9e742120c..6a807f5f96 100644
--- a/default-configs/riscv32-softmmu.mak
+++ b/default-configs/riscv32-softmmu.mak
@@ -1,4 +1,5 @@
-# Default configuration for riscv-softmmu
+# Default configuration for riscv32-softmmu
 
 CONFIG_SERIAL=y
 CONFIG_VIRTIO=y
+CONFIG_SIFIVE_E300=y
diff --git a/default-configs/riscv64-softmmu.mak 
b/default-configs/riscv64-softmmu.mak
index f9e742120c..1a0349fe27 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -1,4 +1,5 @@
-# Default configuration for riscv-softmmu
+# Default configuration for riscv64-softmmu
 
 CONFIG_SERIAL=y
 CONFIG_VIRTIO=y
+CONFIG_SIFIVE_U500=y
diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
index a0c31ae25e..bac5faa603 100644
--- a/hw/riscv/Makefile.objs
+++ b/hw/riscv/Makefile.objs
@@ -1,11 +1,11 @@
 obj-y += riscv_elf.o
 obj-y += riscv_htif.o
 obj-y += riscv_hart.o
-obj-y += sifive_e300.o
+obj-$(CONFIG_SIFIVE_E300) += sifive_e300.o
 obj-y += sifive_clint.o
 obj-y += sifive_prci.o
 obj-y += sifive_plic.o
-obj-y += sifive_u500.o
+obj-$(CONFIG_SIFIVE_U500) += sifive_u500.o
 obj-y += sifive_uart.o
 obj-y += spike_v1_09.o
 obj-y += spike_v1_10.o

-- 
Best regards,
  Antony Pavlov