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[Qemu-devel] [PATCH v3 02/21] RISC-V ELF Machine Definition
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v3 02/21] RISC-V ELF Machine Definition |
Date: |
Wed, 10 Jan 2018 18:21:45 -0800 |
Define RISC-V ELF machine EM_RISCV 243
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
---
include/elf.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index e8a515c..8e457fc 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -112,6 +112,8 @@ typedef int64_t Elf64_Sxword;
#define EM_UNICORE32 110 /* UniCore32 */
+#define EM_RISCV 243 /* RISC-V */
+
/*
* This is an interim value that we will use until the committee comes
* up with a final number.
--
2.7.0
[Qemu-devel] [PATCH v3 05/21] RISC-V CPU Helpers, Michael Clark, 2018/01/10