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Re: [Qemu-devel] [PATCH v3 14/21] SiFive RISC-V PLIC Block
From: |
Antony Pavlov |
Subject: |
Re: [Qemu-devel] [PATCH v3 14/21] SiFive RISC-V PLIC Block |
Date: |
Thu, 11 Jan 2018 12:10:14 +0300 |
On Wed, 10 Jan 2018 18:21:57 -0800
Michael Clark <address@hidden> wrote:
> The PLIC (Platform Level Interrupt Controller) device provides a
> parameterizable interrupt controller based on SiFive's PLIC specification.
>
> Signed-off-by: Michael Clark <address@hidden>
> ---
> hw/riscv/sifive_plic.c | 554
> +++++++++++++++++++++++++++++++++++++++++
> include/hw/riscv/sifive_plic.h | 91 +++++++
> 2 files changed, 645 insertions(+)
> create mode 100644 hw/riscv/sifive_plic.c
> create mode 100644 include/hw/riscv/sifive_plic.h
>
...
> diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h
> new file mode 100644
> index 0000000..e1be499
> --- /dev/null
> +++ b/include/hw/riscv/sifive_plic.h
> @@ -0,0 +1,91 @@
> +/*
> + * SiFive PLIC (Platform Level Interrupt Controller) interface
> + *
> + * Copyright (c) 2017 SiFive, Inc.
> + *
> + * This provides a RISC-V PLIC device
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> copy
> + * of this software and associated documentation files (the "Software"), to
> deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_SIFIVE_PLIC_H
> +#define HW_SIFIVE_PLIC_H
> +
> +#include "hw/irq.h"
> +
> +#define TYPE_SIFIVE_PLIC "riscv.sifive.plic"
> +
> +#define SIFIVE_PLIC(obj) \
> + OBJECT_CHECK(SiFivePLICState, (obj), TYPE_SIFIVE_PLIC)
> +
> +typedef enum PLICMode {
> + PLICMode_U,
> + PLICMode_S,
> + PLICMode_H,
> + PLICMode_M
> +} PLICMode;
> +
> +typedef struct PLICAddr {
> + uint32_t addrid;
> + uint32_t hartid;
> + PLICMode mode;
> +} PLICAddr;
> +
> +typedef struct SiFivePLICState {
> + /*< private >*/
> + SysBusDevice parent_obj;
> +
> + /*< public >*/
> + MemoryRegion mmio;
> + uint32_t num_addrs;
> + uint32_t bitfield_words;
> + PLICAddr *addr_config;
> + uint32_t *source_priority;
> + uint32_t *target_priority;
> + uint32_t *pending;
> + uint32_t *claimed;
> + uint32_t *enable;
> + QemuMutex lock;
> + qemu_irq *irqs;
> +
> + /* config */
> + char *hart_config;
> + uint32_t num_sources;
> + uint32_t num_priorities;
> + uint32_t priority_base;
> + uint32_t pending_base;
> + uint32_t enable_base;
> + uint32_t enable_stride;
> + uint32_t context_base;
> + uint32_t context_stride;
> + uint32_t aperture_size;
> +} SiFivePLICState;
> +
> +void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq);
> +void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq);
> +
> +DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
> + uint32_t num_sources, uint32_t num_priorities,
> + uint32_t priority_base, uint32_t pending_base,
> + uint32_t enable_base, uint32_t enable_stride,
> + uint32_t context_base, uint32_t context_stride,
> + uint32_t aperture_size);
> +
> +#endif
> +
> --
> 2.7.0
'git am' reports on 'new blank line at EOF' here
(include/hw/riscv/sifive_plic.h):
Applying: SiFive RISC-V PLIC Block
.git/rebase-apply/patch:664: new blank line at EOF.
+
warning: 1 line adds whitespace errors.
--
Best regards,
Antony Pavlov
- [Qemu-devel] [PATCH v3 13/21] SiFive RISC-V CLINT Block, (continued)
- [Qemu-devel] [PATCH v3 13/21] SiFive RISC-V CLINT Block, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 11/21] RISC-V HTIF Console, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 18/21] SiFive RISC-V PRCI Block, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 10/21] RISC-V Linux User Emulation, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 17/21] SiFive RISC-V UART Device, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 16/21] RISC-V VirtIO Machine, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 21/21] RISC-V Build Infrastructure, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 14/21] SiFive RISC-V PLIC Block, Michael Clark, 2018/01/10
- Re: [Qemu-devel] [PATCH v3 14/21] SiFive RISC-V PLIC Block,
Antony Pavlov <=
- [Qemu-devel] [PATCH v3 04/21] RISC-V Disassembler, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 19/21] SiFive Freedom E300 RISC-V Machine, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 15/21] RISC-V Spike Machines, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 20/21] SiFive Freedom U500 RISC-V Machine, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation, Michael Clark, 2018/01/10