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[Qemu-devel] [PULL 21/24] sdhci: fix CAPAB/MAXCURR registers, both are 6
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 21/24] sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only |
Date: |
Tue, 16 Jan 2018 13:34:16 +0000 |
From: Philippe Mathieu-Daudé <address@hidden>
running qtests:
$ make check-qtest-arm
GTESTER check-qtest-arm
SDHC rd_4b @0x44 not implemented
SDHC wr_4b @0x40 <- 0x89abcdef not implemented
SDHC wr_4b @0x44 <- 0x01234567 not implemented
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
include/hw/sd/sdhci.h | 4 ++--
hw/sd/sdhci.c | 23 +++++++++++++++++++----
2 files changed, 21 insertions(+), 6 deletions(-)
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index 8041c96..442e30a 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -72,8 +72,8 @@ typedef struct SDHCIState {
uint64_t admasysaddr; /* ADMA System Address Register */
/* Read-only registers */
- uint32_t capareg; /* Capabilities Register */
- uint32_t maxcurr; /* Maximum Current Capabilities Register */
+ uint64_t capareg; /* Capabilities Register */
+ uint64_t maxcurr; /* Maximum Current Capabilities Register */
uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */
uint32_t buf_maxsz;
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index c4e486e..d4fcebc 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -899,10 +899,16 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset,
unsigned size)
ret = s->acmd12errsts;
break;
case SDHC_CAPAB:
- ret = s->capareg;
+ ret = (uint32_t)s->capareg;
+ break;
+ case SDHC_CAPAB + 4:
+ ret = (uint32_t)(s->capareg >> 32);
break;
case SDHC_MAXCURR:
- ret = s->maxcurr;
+ ret = (uint32_t)s->maxcurr;
+ break;
+ case SDHC_MAXCURR + 4:
+ ret = (uint32_t)(s->maxcurr >> 32);
break;
case SDHC_ADMAERR:
ret = s->admaerr;
@@ -1123,6 +1129,15 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
}
sdhci_update_irq(s);
break;
+
+ case SDHC_CAPAB:
+ case SDHC_CAPAB + 4:
+ case SDHC_MAXCURR:
+ case SDHC_MAXCURR + 4:
+ qemu_log_mask(LOG_GUEST_ERROR, "SDHC wr_%ub @0x%02" HWADDR_PRIx
+ " <- 0x%08x read-only\n", size, offset, value >> shift);
+ break;
+
default:
qemu_log_mask(LOG_UNIMP, "SDHC wr_%ub @0x%02" HWADDR_PRIx " <- 0x%08x "
"not implemented\n", size, offset, value >> shift);
@@ -1163,8 +1178,8 @@ static inline unsigned int sdhci_get_fifolen(SDHCIState
*s)
#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
/* Capabilities registers provide information on supported features
* of this specific host controller implementation */ \
- DEFINE_PROP_UINT32("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \
- DEFINE_PROP_UINT32("maxcurr", _state, maxcurr, 0)
+ DEFINE_PROP_UINT64("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \
+ DEFINE_PROP_UINT64("maxcurr", _state, maxcurr, 0)
static void sdhci_initfn(SDHCIState *s)
{
--
2.7.4
- [Qemu-devel] [PULL 15/24] sdhci: refactor common sysbus/pci realize() into sdhci_common_realize(), (continued)
- [Qemu-devel] [PULL 15/24] sdhci: refactor common sysbus/pci realize() into sdhci_common_realize(), Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 06/24] hw/sd/milkymist-memcard: Reset SD card on controller reset, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 02/24] get_phys_addr_pmsav7: Support AP=0b111 for v7M, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 08/24] hw/sd/omap_mmc: Reset SD card on controller reset, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 05/24] hw/sd/pl181: Reset SD card on controller reset, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 13/24] sdhci: use DEFINE_SDHCI_COMMON_PROPERTIES() for common sysbus/pci properties, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 14/24] sdhci: refactor common sysbus/pci class_init() into sdhci_common_class_init(), Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 20/24] sdhci: rename the SDHC_CAPAB register, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 23/24] sdhci: fix the PCI device, using the PCI address space for DMA, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 22/24] sdhci: Implement write method of ACMD12ERRSTS register, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 21/24] sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only,
Peter Maydell <=
- [Qemu-devel] [PULL 11/24] sdhci: clean up includes, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 01/24] hw/intc/armv7m: Support byte and halfword accesses to CFSR, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 16/24] sdhci: refactor common sysbus/pci unrealize() into sdhci_common_unrealize(), Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 17/24] sdhci: use qemu_log_mask(UNIMP) instead of fprintf(), Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 18/24] sdhci: convert the DPRINT() calls into trace events, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 24/24] sdhci: add a 'dma' property to the sysbus devices, Peter Maydell, 2018/01/16
- Re: [Qemu-devel] [PULL 00/24] target-arm queue, Peter Maydell, 2018/01/16