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[Qemu-devel] [PULL 01/24] hw/intc/armv7m: Support byte and halfword acce
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 01/24] hw/intc/armv7m: Support byte and halfword accesses to CFSR |
Date: |
Tue, 16 Jan 2018 13:33:56 +0000 |
The Configurable Fault Status Register for ARMv7M and v8M is
supposed to be byte and halfword accessible, but we were only
implementing word accesses. Add support for the other access
sizes, which are used by the Zephyr RTOS.
Signed-off-by: Peter Maydell <address@hidden>
Reported-by: Andy Gross <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Message-id: address@hidden
---
hw/intc/armv7m_nvic.c | 38 ++++++++++++++++++++++----------------
1 file changed, 22 insertions(+), 16 deletions(-)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index dd49b6c..8ca6cee 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -896,13 +896,6 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset,
MemTxAttrs attrs)
val |= (1 << 8);
}
return val;
- case 0xd28: /* Configurable Fault Status. */
- /* The BFSR bits [15:8] are shared between security states
- * and we store them in the NS copy
- */
- val = cpu->env.v7m.cfsr[attrs.secure];
- val |= cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK;
- return val;
case 0xd2c: /* Hard Fault Status. */
return cpu->env.v7m.hfsr;
case 0xd30: /* Debug Fault Status. */
@@ -1280,15 +1273,6 @@ static void nvic_writel(NVICState *s, uint32_t offset,
uint32_t value,
s->vectors[ARMV7M_EXCP_DEBUG].active = (value & (1 << 8)) != 0;
nvic_irq_update(s);
break;
- case 0xd28: /* Configurable Fault Status. */
- cpu->env.v7m.cfsr[attrs.secure] &= ~value; /* W1C */
- if (attrs.secure) {
- /* The BFSR bits [15:8] are shared between security states
- * and we store them in the NS copy.
- */
- cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK);
- }
- break;
case 0xd2c: /* Hard Fault Status. */
cpu->env.v7m.hfsr &= ~value; /* W1C */
break;
@@ -1667,6 +1651,14 @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr
addr,
val = deposit32(val, i * 8, 8, get_prio(s, hdlidx, sbank));
}
break;
+ case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */
+ /* The BFSR bits [15:8] are shared between security states
+ * and we store them in the NS copy
+ */
+ val = s->cpu->env.v7m.cfsr[attrs.secure];
+ val |= s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK;
+ val = extract32(val, (offset - 0xd28) * 8, size * 8);
+ break;
case 0xfe0 ... 0xfff: /* ID. */
if (offset & 3) {
val = 0;
@@ -1765,6 +1757,20 @@ static MemTxResult nvic_sysreg_write(void *opaque,
hwaddr addr,
}
nvic_irq_update(s);
return MEMTX_OK;
+ case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */
+ /* All bits are W1C, so construct 32 bit value with 0s in
+ * the parts not written by the access size
+ */
+ value <<= ((offset - 0xd28) * 8);
+
+ s->cpu->env.v7m.cfsr[attrs.secure] &= ~value;
+ if (attrs.secure) {
+ /* The BFSR bits [15:8] are shared between security states
+ * and we store them in the NS copy.
+ */
+ s->cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK);
+ }
+ return MEMTX_OK;
}
if (size == 4) {
nvic_writel(s, offset, value, attrs);
--
2.7.4
- [Qemu-devel] [PULL 02/24] get_phys_addr_pmsav7: Support AP=0b111 for v7M, (continued)
- [Qemu-devel] [PULL 02/24] get_phys_addr_pmsav7: Support AP=0b111 for v7M, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 08/24] hw/sd/omap_mmc: Reset SD card on controller reset, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 05/24] hw/sd/pl181: Reset SD card on controller reset, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 13/24] sdhci: use DEFINE_SDHCI_COMMON_PROPERTIES() for common sysbus/pci properties, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 14/24] sdhci: refactor common sysbus/pci class_init() into sdhci_common_class_init(), Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 20/24] sdhci: rename the SDHC_CAPAB register, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 23/24] sdhci: fix the PCI device, using the PCI address space for DMA, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 22/24] sdhci: Implement write method of ACMD12ERRSTS register, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 21/24] sdhci: fix CAPAB/MAXCURR registers, both are 64bit and read-only, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 11/24] sdhci: clean up includes, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 01/24] hw/intc/armv7m: Support byte and halfword accesses to CFSR,
Peter Maydell <=
- [Qemu-devel] [PULL 16/24] sdhci: refactor common sysbus/pci unrealize() into sdhci_common_unrealize(), Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 17/24] sdhci: use qemu_log_mask(UNIMP) instead of fprintf(), Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 18/24] sdhci: convert the DPRINT() calls into trace events, Peter Maydell, 2018/01/16
- [Qemu-devel] [PULL 24/24] sdhci: add a 'dma' property to the sysbus devices, Peter Maydell, 2018/01/16
- Re: [Qemu-devel] [PULL 00/24] target-arm queue, Peter Maydell, 2018/01/16