On 17 January 2018 at 15:23, Marcel Apfelbaum <address@hidden> wrote:
On 16/01/2018 16:34, Peter Maydell wrote:
On 16 January 2018 at 01:37, Andrey Smirnov <address@hidden>
I'm not familiar enough with our PCI code to be able to review
this, I'm afraid. MST and Marcel are our PCI subsystem maintainers --
could one of you have a look at whether this seems to be a correct
implementation of a pcie host controller ?
Sadly PCI Host bridges do not have a standard, each HW vendor
can do pretty much what they want.
That being said, if Andrey can point me to the PCI spec for the Designware
PCI host bridge and what parts they implemented for it I can have a look,
sure.
I'm not so worried about whether it's implementing the spec for
the hardware (I trust Andrey has done enough testing for that
side of things), but whether the code seems to be structured
the way we expect a QEMU pcie host controller to be structured,
is using the right APIs, and so on.