Re: [Qemu-devel] [PATCH v2 05/16] target/arm: Change the type of vfp.regs

[Alex Bennée]

Richard Henderson <address@hidden> writes:

> All direct users of this field want an integral value.  Drop all
> of the extra casting between uint64_t and float64.

Did the extra casting ever generate superfluous code?

Anyway:

Reviewed-by: Alex Bennée <address@hidden>

>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  target/arm/cpu.h           |  2 +-
>  target/arm/arch_dump.c     |  4 ++--
>  target/arm/helper.c        | 20 ++++++++++----------
>  target/arm/machine.c       |  2 +-
>  target/arm/translate-a64.c |  8 ++++----
>  target/arm/translate.c     |  2 +-
>  6 files changed, 19 insertions(+), 19 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 96316700dd..76ab7953a6 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -492,7 +492,7 @@ typedef struct CPUARMState {
>           * the two execution states, and means we do not need to explicitly
>           * map these registers when changing states.
>           */
> -        float64 regs[64];
> +        uint64_t regs[64];
>
>          uint32_t xregs[16];
>          /* We store these fpcsr fields separately for convenience.  */
> diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
> index 9e5b2fb31c..0c43e0eef8 100644
> --- a/target/arm/arch_dump.c
> +++ b/target/arm/arch_dump.c
> @@ -100,7 +100,7 @@ static int 
> aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
>      aarch64_note_init(&note, s, "CORE", 5, NT_PRFPREG, sizeof(note.vfp));
>
>      for (i = 0; i < 64; ++i) {
> -        note.vfp.vregs[i] = cpu_to_dump64(s, float64_val(env->vfp.regs[i]));
> +        note.vfp.vregs[i] = cpu_to_dump64(s, env->vfp.regs[i]);
>      }
>
>      if (s->dump_info.d_endian == ELFDATA2MSB) {
> @@ -229,7 +229,7 @@ static int arm_write_elf32_vfp(WriteCoreDumpFunction f, 
> CPUARMState *env,
>      arm_note_init(&note, s, "LINUX", 6, NT_ARM_VFP, sizeof(note.vfp));
>
>      for (i = 0; i < 32; ++i) {
> -        note.vfp.vregs[i] = cpu_to_dump64(s, float64_val(env->vfp.regs[i]));
> +        note.vfp.vregs[i] = cpu_to_dump64(s, env->vfp.regs[i]);
>      }
>
>      note.vfp.fpscr = cpu_to_dump32(s, vfp_get_fpscr(env));
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index c83c901a86..8fda797582 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -64,15 +64,15 @@ static int vfp_gdb_get_reg(CPUARMState *env, uint8_t 
> *buf, int reg)
>      /* VFP data registers are always little-endian.  */
>      nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
>      if (reg < nregs) {
> -        stfq_le_p(buf, env->vfp.regs[reg]);
> +        stq_le_p(buf, env->vfp.regs[reg]);
>          return 8;
>      }
>      if (arm_feature(env, ARM_FEATURE_NEON)) {
>          /* Aliases for Q regs.  */
>          nregs += 16;
>          if (reg < nregs) {
> -            stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
> -            stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
> +            stq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
> +            stq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
>              return 16;
>          }
>      }
> @@ -90,14 +90,14 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t 
> *buf, int reg)
>
>      nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
>      if (reg < nregs) {
> -        env->vfp.regs[reg] = ldfq_le_p(buf);
> +        env->vfp.regs[reg] = ldq_le_p(buf);
>          return 8;
>      }
>      if (arm_feature(env, ARM_FEATURE_NEON)) {
>          nregs += 16;
>          if (reg < nregs) {
> -            env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
> -            env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
> +            env->vfp.regs[(reg - 32) * 2] = ldq_le_p(buf);
> +            env->vfp.regs[(reg - 32) * 2 + 1] = ldq_le_p(buf + 8);
>              return 16;
>          }
>      }
> @@ -114,8 +114,8 @@ static int aarch64_fpu_gdb_get_reg(CPUARMState *env, 
> uint8_t *buf, int reg)
>      switch (reg) {
>      case 0 ... 31:
>          /* 128 bit FP register */
> -        stfq_le_p(buf, env->vfp.regs[reg * 2]);
> -        stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
> +        stq_le_p(buf, env->vfp.regs[reg * 2]);
> +        stq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
>          return 16;
>      case 32:
>          /* FPSR */
> @@ -135,8 +135,8 @@ static int aarch64_fpu_gdb_set_reg(CPUARMState *env, 
> uint8_t *buf, int reg)
>      switch (reg) {
>      case 0 ... 31:
>          /* 128 bit FP register */
> -        env->vfp.regs[reg * 2] = ldfq_le_p(buf);
> -        env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
> +        env->vfp.regs[reg * 2] = ldq_le_p(buf);
> +        env->vfp.regs[reg * 2 + 1] = ldq_le_p(buf + 8);
>          return 16;
>      case 32:
>          /* FPSR */
> diff --git a/target/arm/machine.c b/target/arm/machine.c
> index 176274629c..a85c2430d3 100644
> --- a/target/arm/machine.c
> +++ b/target/arm/machine.c
> @@ -50,7 +50,7 @@ static const VMStateDescription vmstate_vfp = {
>      .minimum_version_id = 3,
>      .needed = vfp_needed,
>      .fields = (VMStateField[]) {
> -        VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64),
> +        VMSTATE_UINT64_ARRAY(env.vfp.regs, ARMCPU, 64),
>          /* The xregs array is a little awkward because element 1 (FPSCR)
>           * requires a specific accessor, so we have to split it up in
>           * the vmstate:
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 6d9b3af64c..c14fb4185c 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -165,12 +165,12 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
>      if (flags & CPU_DUMP_FPU) {
>          int numvfpregs = 32;
>          for (i = 0; i < numvfpregs; i += 2) {
> -            uint64_t vlo = float64_val(env->vfp.regs[i * 2]);
> -            uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]);
> +            uint64_t vlo = env->vfp.regs[i * 2];
> +            uint64_t vhi = env->vfp.regs[(i * 2) + 1];
>              cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 " ",
>                          i, vhi, vlo);
> -            vlo = float64_val(env->vfp.regs[(i + 1) * 2]);
> -            vhi = float64_val(env->vfp.regs[((i + 1) * 2) + 1]);
> +            vlo = env->vfp.regs[(i + 1) * 2];
> +            vhi = env->vfp.regs[((i + 1) * 2) + 1];
>              cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "\n",
>                          i + 1, vhi, vlo);
>          }
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 852d2a75b1..cfe49bf579 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -12572,7 +12572,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, 
> fprintf_function cpu_fprintf,
>              numvfpregs += 16;
>          }
>          for (i = 0; i < numvfpregs; i++) {
> -            uint64_t v = float64_val(env->vfp.regs[i]);
> +            uint64_t v = env->vfp.regs[i];
>              cpu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n",
>                          i * 2, (uint32_t)v,
>                          i * 2 + 1, (uint32_t)(v >> 32),


--
Alex Bennée