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Re: [Qemu-devel] [PATCH v8 03/14] sdhci: implement the Host Control 2 re
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH v8 03/14] sdhci: implement the Host Control 2 register (tuning sequence) |
Date: |
Tue, 23 Jan 2018 14:37:33 -0800 |
On Mon, Jan 22, 2018 at 7:06 PM, Philippe Mathieu-Daudé <address@hidden> wrote:
> [based on a patch from Alistair Francis <address@hidden>
> from qemu/xilinx tag xilinx-v2015.2]
> Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
> hw/sd/sdhci-internal.h | 10 ++++++++++
> include/hw/sd/sdhci.h | 1 +
> hw/sd/sdhci.c | 22 +++++++++++++++++++---
> 3 files changed, 30 insertions(+), 3 deletions(-)
>
> diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
> index 9111f6856a..e7cbea297f 100644
> --- a/hw/sd/sdhci-internal.h
> +++ b/hw/sd/sdhci-internal.h
> @@ -184,6 +184,16 @@ FIELD(SDHC_ACMD12ERRSTS, TIMEOUT_ERR, 1, 1);
> FIELD(SDHC_ACMD12ERRSTS, CRC_ERR, 2, 1);
> FIELD(SDHC_ACMD12ERRSTS, INDEX_ERR, 4, 1);
>
> +/* Host Control Register 2 (since v3) */
> +#define SDHC_HOSTCTL2 0x3E
> +FIELD(SDHC_HOSTCTL2, UHS_MODE_SEL, 0, 3);
> +FIELD(SDHC_HOSTCTL2, V18_ENA, 3, 1); /* UHS-I only */
> +FIELD(SDHC_HOSTCTL2, DRIVER_STRENGTH, 4, 2); /* UHS-I only */
> +FIELD(SDHC_HOSTCTL2, EXECUTE_TUNING, 6, 1); /* UHS-I only */
> +FIELD(SDHC_HOSTCTL2, SAMPLING_CLKSEL, 7, 1); /* UHS-I only */
> +FIELD(SDHC_HOSTCTL2, ASYNC_INT, 14, 1);
> +FIELD(SDHC_HOSTCTL2, PRESET_ENA, 15, 1);
> +
> /* HWInit Capabilities Register 0x05E80080 */
> #define SDHC_CAPAB 0x40
> FIELD(SDHC_CAPAB, TOCLKFREQ, 0, 6);
> diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
> index 5af9e0dc5a..0fff941a98 100644
> --- a/include/hw/sd/sdhci.h
> +++ b/include/hw/sd/sdhci.h
> @@ -71,6 +71,7 @@ typedef struct SDHCIState {
> uint16_t norintsigen; /* Normal Interrupt Signal Enable Register */
> uint16_t errintsigen; /* Error Interrupt Signal Enable Register */
> uint16_t acmd12errsts; /* Auto CMD12 error status register */
> + uint16_t hostctl2; /* Host Control 2 */
> uint64_t admasysaddr; /* ADMA System Address Register */
>
> /* Read-only registers */
> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> index 013c35e585..b7e69fbc22 100644
> --- a/hw/sd/sdhci.c
> +++ b/hw/sd/sdhci.c
> @@ -408,14 +408,29 @@ static void sdhci_end_transfer(SDHCIState *s)
> static void sdhci_read_block_from_card(SDHCIState *s)
> {
> int index = 0;
> + uint8_t data;
> + const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK;
>
> if ((s->trnmod & SDHC_TRNS_MULTI) &&
> (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) {
> return;
> }
>
> - for (index = 0; index < (s->blksize & BLOCK_SIZE_MASK); index++) {
> - s->fifo_buffer[index] = sdbus_read_data(&s->sdbus);
> + for (index = 0; index < blk_size; index++) {
> + data = sdbus_read_data(&s->sdbus);
> + if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
> + /* Device is not in tunning */
> + s->fifo_buffer[index] = data;
> + }
> + }
> +
> + if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
> + /* Device is in tunning */
> + s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK;
> + s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK;
> + s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ |
> + SDHC_DATA_INHIBIT);
> + goto read_done;
> }
>
> /* New data now available for READ through Buffer Port Register */
> @@ -440,6 +455,7 @@ static void sdhci_read_block_from_card(SDHCIState *s)
> }
> }
>
> +read_done:
> sdhci_update_irq(s);
> }
>
> @@ -1005,7 +1021,7 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset,
> unsigned size)
> ret = s->norintsigen | (s->errintsigen << 16);
> break;
> case SDHC_ACMD12ERRSTS:
> - ret = s->acmd12errsts;
> + ret = s->acmd12errsts | (s->hostctl2 << 16);
> break;
> case SDHC_CAPAB:
> ret = (uint32_t)s->capareg;
> --
> 2.15.1
>
>
- [Qemu-devel] [PATCH v8 00/14] SDHCI: add tuning sequence for UHS-I cards (part 3), Philippe Mathieu-Daudé, 2018/01/22
- [Qemu-devel] [PATCH v8 01/14] sdhci: add support for v3 capabilities, Philippe Mathieu-Daudé, 2018/01/22
- [Qemu-devel] [PATCH v8 02/14] sdhci: rename the hostctl1 register, Philippe Mathieu-Daudé, 2018/01/22
- [Qemu-devel] [PATCH v8 03/14] sdhci: implement the Host Control 2 register (tuning sequence), Philippe Mathieu-Daudé, 2018/01/22
- Re: [Qemu-devel] [PATCH v8 03/14] sdhci: implement the Host Control 2 register (tuning sequence),
Alistair Francis <=
- [Qemu-devel] [PATCH v8 04/14] sdbus: add trace events, Philippe Mathieu-Daudé, 2018/01/22
- [Qemu-devel] [PATCH v8 05/14] sdhci: implement UHS-I voltage switch, Philippe Mathieu-Daudé, 2018/01/22
- [Qemu-devel] [PATCH v8 06/14] sdhci: implement CMD/DAT[] fields in the Present State register, Philippe Mathieu-Daudé, 2018/01/22
- [Qemu-devel] [PATCH v8 07/14] hw/arm/bcm2835_peripherals: implement SDHCI Spec. v3, Philippe Mathieu-Daudé, 2018/01/22
- [Qemu-devel] [PATCH v8 08/14] hw/arm/bcm2835_peripherals: change maximum block size to 1kB, Philippe Mathieu-Daudé, 2018/01/22