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[Qemu-devel] [PULL 14/21] hw/intc/arm_gic: Prevent the GIC from signalin
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 14/21] hw/intc/arm_gic: Prevent the GIC from signaling an IRQ when it's "active and pending" |
Date: |
Thu, 25 Jan 2018 13:43:22 +0000 |
From: Luc MICHEL <address@hidden>
In the GIC, when an IRQ is acknowledged, its state goes from "pending"
to:
- "active" if the corresponding IRQ pin has been de-asserted
- "active and pending" otherwise.
The GICv2 manual states that when a IRQ becomes active (or active and
pending), the GIC should either signal another (higher priority) IRQ to
the CPU if there is one, or de-assert the CPU IRQ pin.
The current implementation of the GIC in QEMU does not check if the
IRQ is already active when looking for pending interrupts with
sufficient priority in gic_update(). This can lead to signaling an
interrupt that is already active.
This usually happens when splitting priority drop and interrupt
deactivation. On priority drop, the IRQ stays active until deactivation.
If it becomes pending again, chances are that it will be incorrectly
selected as best_irq in gic_update().
This commit fixes this by checking if the IRQ is not already active when
looking for best_irq in gic_update().
Note that regarding the ARM11MPCore GIC version, the corresponding
manual is not clear on that point, but it has has no priority
drop/interrupt deactivation separation, so this case should not happen.
Signed-off-by: Luc MICHEL <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index d701e49..dad383e 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -93,6 +93,7 @@ void gic_update(GICState *s)
best_irq = 1023;
for (irq = 0; irq < s->num_irq; irq++) {
if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) &&
+ (!GIC_TEST_ACTIVE(irq, cm)) &&
(irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) {
if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
best_prio = GIC_GET_PRIORITY(irq, cpu);
--
2.7.4
- [Qemu-devel] [PULL 02/21] i.MX: Fix FEC/ENET receive funtions, (continued)
- [Qemu-devel] [PULL 02/21] i.MX: Fix FEC/ENET receive funtions, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 04/21] target/arm: Use pointers in crypto helpers, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 11/21] target/arm: Move cpu_get_tb_cpu_state out of line, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 15/21] hw/intc/arm_gic: Fix C_RPR value on idle priority, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 16/21] hw/intc/arm_gic: Fix group priority computation for group 1 IRQs, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 18/21] hw/arm/virt: Check that the CPU realize method succeeded, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 05/21] target/arm: Use pointers in neon zip/uzp helpers, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 19/21] sdhci: fix a NULL pointer dereference due to uninitialized AddresSpace object, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 21/21] pl110: Implement vertical compare/next base interrupts, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 17/21] hw/intc/arm_gic: Fix the NS view of C_BPR when C_CTRL.CBPR is 1, Peter Maydell, 2018/01/25
- [Qemu-devel] [PULL 14/21] hw/intc/arm_gic: Prevent the GIC from signaling an IRQ when it's "active and pending",
Peter Maydell <=
- [Qemu-devel] [PULL 20/21] xilinx_spips: Correct usage of an uninitialized local variable, Peter Maydell, 2018/01/25
- Re: [Qemu-devel] [PULL 00/21] target-arm queue, no-reply, 2018/01/25
- Re: [Qemu-devel] [PULL 00/21] target-arm queue, Peter Maydell, 2018/01/25