Re: [Qemu-devel] [PATCH v10.5 12/20] target/arm: Use vector infrastructure for aa64 add/sub/logic

[Peter Maydell]

On 17 January 2018 at 16:14, Richard Henderson
<address@hidden> wrote:
> Reviewed-by: Alex Bennée <address@hidden>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  target/arm/translate-a64.c | 207 
> +++++++++++++++++++++++++++++----------------
>  1 file changed, 134 insertions(+), 73 deletions(-)
>
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index 70c1e08a36..b97bc9b83c 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -21,6 +21,7 @@
>  #include "cpu.h"
>  #include "exec/exec-all.h"
>  #include "tcg-op.h"
> +#include "tcg-op-gvec.h"
>  #include "qemu/log.h"
>  #include "arm_ldst.h"
>  #include "translate.h"
> @@ -83,6 +84,10 @@ typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64);
>  typedef void CryptoTwoOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32);
>  typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32);
>
> +/* Note that the gvec expanders operate on offsets + sizes.  */
> +typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
> +                        uint32_t, uint32_t, uint32_t);
> +
>  /* initialize TCG globals.  */
>  void a64_translate_init(void)
>  {
> @@ -535,6 +540,21 @@ static inline int vec_reg_offset(DisasContext *s, int 
> regno,
>      return offs;
>  }
>
> +/* Return the offset info CPUARMState of the "whole" vector register Qn.  */
> +static inline int vec_full_reg_offset(DisasContext *s, int regno)
> +{
> +    assert_fp_access_checked(s);
> +    return offsetof(CPUARMState, vfp.regs[regno * 2]);
> +}

This function is already in the preparatory SVE code in target-arm.next,
so it should go away on rebase...

> +
> +/* Return the byte size of the "whole" vector register, VL / 8.  */
> +static inline int vec_full_reg_size(DisasContext *s)
> +{
> +    /* FIXME SVE: We should put the composite ZCR_EL* value into tb->flags.
> +       In the meantime this is just the AdvSIMD length of 128.  */
> +    return 128 / 8;
> +}

...and this is fixed in your other patchset with the leftovers from
that preparatory set, right? What's the plan for what sequence we
put these into master?

Have you done risu-testing on this patchset?

Otherwise
Reviewed-by: Peter Maydell <address@hidden>

thanks
-- PMM