Re: [Qemu-devel] [PATCH 3/3] s390x/pci: use the right pal and pba in reg_ioat()

[Cornelia Huck]

On Tue, 30 Jan 2018 10:47:15 +0100
Yi Min Zhao <address@hidden> wrote:

> When registering ioat, pba should be comprised of leftmost 52 bits and
> rightmost 12 binary zeros, and pal should be comprised of leftmost 52
> bits and right most 12 binary ones. Let's fixup this.
> 
> Reviewed-by: Pierre Morel <address@hidden>
> Signed-off-by: Yi Min Zhao <address@hidden>
> ---
>  hw/s390x/s390-pci-inst.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
> index 997a9cc2e9..3fcc330fe3 100644
> --- a/hw/s390x/s390-pci-inst.c
> +++ b/hw/s390x/s390-pci-inst.c
> @@ -865,6 +865,8 @@ static int reg_ioat(CPUS390XState *env, S390PCIIOMMU 
> *iommu, ZpciFib fib,
>      uint8_t dt = (g_iota >> 2) & 0x7;
>      uint8_t t = (g_iota >> 11) & 0x1;
>  
> +    pba &= ~0xfff;
> +    pal |= 0xfff;
>      if (pba > pal || pba < ZPCI_SDMA_ADDR || pal > ZPCI_EDMA_ADDR) {
>          s390_program_interrupt(env, PGM_OPERAND, 6, ra);
>          return -EINVAL;

It seems like pba and pal are part of the fib, which in turn seems to
be provided by the caller. Is that correct? If yes, is it valid for
them to not have the rightmost 12 bits as 0s resp. 1s?

(Probably answered in the architecture, I know. Might make sense to be
a tad more explicit in the description.)