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[Qemu-devel] [PATCH v8 05/14] hw/arm/smmuv3: Wired IRQ and GERROR helper
From: |
Eric Auger |
Subject: |
[Qemu-devel] [PATCH v8 05/14] hw/arm/smmuv3: Wired IRQ and GERROR helpers |
Date: |
Mon, 5 Feb 2018 14:39:23 +0100 |
We introduce some helpers to handle wired IRQs and especially
GERROR interrupt. SMMU writes GERROR register on GERROR event
and SW acks GERROR interrupts by setting GERRORn.
The Wired interrupts are edge sensitive hence the pulse usage.
Signed-off-by: Eric Auger <address@hidden>
---
v7 -> v8:
- remove SMMU_PENDING_GERRORS macro
- properly toggle gerror
- properly sanitize gerrorn write
---
hw/arm/smmuv3-internal.h | 10 ++++++++
hw/arm/smmuv3.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++
hw/arm/trace-events | 3 +++
3 files changed, 77 insertions(+)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 84a15c1..72d9c6c 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -152,4 +152,14 @@ static inline uint64_t smmu_read64(uint64_t r, unsigned
offset,
return extract64(r, offset << 3, 32);
}
+/* Interrupts */
+
+#define smmuv3_eventq_irq_enabled(s) \
+ (FIELD_EX32(s->irq_ctrl, IRQ_CTRL, EVENTQ_IRQEN))
+#define smmuv3_gerror_irq_enabled(s) \
+ (FIELD_EX32(s->irq_ctrl, IRQ_CTRL, GERROR_IRQEN))
+
+void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, uint32_t gerror_mask);
+void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t gerrorn);
+
#endif
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index c9a13b0..6bad7e8 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -30,6 +30,70 @@
#include "hw/arm/smmuv3.h"
#include "smmuv3-internal.h"
+/**
+ * smmuv3_trigger_irq - pulse @irq if enabled and update
+ * GERROR register in case of GERROR interrupt
+ *
+ * @irq: irq type
+ * @gerror_mask: mask of gerrors to toggle (relevant if @irq is GERROR)
+ */
+void smmuv3_trigger_irq(SMMUv3State *s, SMMUIrq irq, uint32_t gerror_mask)
+{
+
+ bool pulse = false;
+
+ switch (irq) {
+ case SMMU_IRQ_EVTQ:
+ pulse = smmuv3_eventq_irq_enabled(s);
+ break;
+ case SMMU_IRQ_PRIQ:
+ error_setg(&error_fatal, "PRI not supported");
+ break;
+ case SMMU_IRQ_CMD_SYNC:
+ pulse = true;
+ break;
+ case SMMU_IRQ_GERROR:
+ {
+ uint32_t pending = s->gerror ^ s->gerrorn;
+ uint32_t new_gerrors = ~pending & gerror_mask;
+
+ if (!new_gerrors) {
+ /* only toggle non pending errors */
+ return;
+ }
+ s->gerror ^= new_gerrors;
+ trace_smmuv3_write_gerror(new_gerrors, s->gerror);
+
+ /* pulse the GERROR irq only if all previous gerrors were acked */
+ pulse = smmuv3_gerror_irq_enabled(s) && !pending;
+ break;
+ }
+ }
+ if (pulse) {
+ trace_smmuv3_trigger_irq(irq);
+ qemu_irq_pulse(s->irq[irq]);
+ }
+}
+
+void smmuv3_write_gerrorn(SMMUv3State *s, uint32_t new_gerrorn)
+{
+ uint32_t pending = s->gerror ^ s->gerrorn;
+ uint32_t toggled = s->gerrorn ^ new_gerrorn;
+ uint32_t acked;
+
+ if (toggled & ~pending) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "guest toggles non pending errors = 0x%x\n",
+ toggled & ~pending);
+ }
+
+ /* Make sure SW does not toggle irqs that are not active */
+ acked = toggled & pending;
+ s->gerrorn ^= acked;
+
+ trace_smmuv3_write_gerrorn(acked, s->gerrorn);
+}
+
static void smmuv3_init_regs(SMMUv3State *s)
{
/**
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
index 8affbf7..957a67e 100644
--- a/hw/arm/trace-events
+++ b/hw/arm/trace-events
@@ -17,3 +17,6 @@ smmu_set_translated_address(hwaddr iova, hwaddr pa) "iova =
0x%"PRIx64" -> pa =
#hw/arm/smmuv3.c
smmuv3_read_mmio(hwaddr addr, uint64_t val, unsigned size) "addr: 0x%"PRIx64"
val:0x%"PRIx64" size: 0x%x"
+smmuv3_trigger_irq(int irq) "irq=%d"
+smmuv3_write_gerror(uint32_t toggled, uint32_t gerror) "toggled=0x%x, new
gerror=0x%x"
+smmuv3_write_gerrorn(uint32_t acked, uint32_t gerrorn) "acked=0x%x, new
gerrorn=0x%x"
--
2.5.5
- [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support, Eric Auger, 2018/02/05
- [Qemu-devel] [PATCH v8 01/14] hw/arm/smmu-common: smmu base device and datatypes, Eric Auger, 2018/02/05
- [Qemu-devel] [PATCH v8 02/14] hw/arm/smmu-common: IOMMU memory region and address space setup, Eric Auger, 2018/02/05
- [Qemu-devel] [PATCH v8 03/14] hw/arm/smmu-common: VMSAv8-64 page table walk, Eric Auger, 2018/02/05
- [Qemu-devel] [PATCH v8 04/14] hw/arm/smmuv3: Skeleton, Eric Auger, 2018/02/05
- [Qemu-devel] [PATCH v8 05/14] hw/arm/smmuv3: Wired IRQ and GERROR helpers,
Eric Auger <=
- [Qemu-devel] [PATCH v8 06/14] hw/arm/smmuv3: Queue helpers, Eric Auger, 2018/02/05
- [Qemu-devel] [PATCH v8 07/14] hw/arm/smmuv3: Implement MMIO write operations, Eric Auger, 2018/02/05
- [Qemu-devel] [PATCH v8 08/14] hw/arm/smmuv3: Event queue recording helper, Eric Auger, 2018/02/05
- [Qemu-devel] [PATCH v8 09/14] hw/arm/smmuv3: Implement translate callback, Eric Auger, 2018/02/05
- [Qemu-devel] [PATCH v8 10/14] hw/arm/smmuv3: Abort on vfio or vhost case, Eric Auger, 2018/02/05
- [Qemu-devel] [PATCH v8 11/14] target/arm/kvm: Translate the MSI doorbell in kvm_arch_fixup_msi_route, Eric Auger, 2018/02/05
- [Qemu-devel] [PATCH v8 12/14] hw/arm/virt: Add SMMUv3 to the virt board, Eric Auger, 2018/02/05
- [Qemu-devel] [PATCH v8 13/14] hw/arm/virt-acpi-build: Add smmuv3 node in IORT table, Eric Auger, 2018/02/05
- [Qemu-devel] [PATCH v8 14/14] hw/arm/virt: Handle iommu in 2.12 machine type, Eric Auger, 2018/02/05
- Re: [Qemu-devel] [PATCH v8 00/14] ARM SMMUv3 Emulation Support, no-reply, 2018/02/05