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Re: [Qemu-devel] [PATCH v4 06/22] RISC-V FPU Support
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-devel] [PATCH v4 06/22] RISC-V FPU Support |
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Date: |
Mon, 5 Feb 2018 06:01:00 -0800 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.2 |
On 02/04/2018 10:22 PM, Michael Clark wrote:
> +uint64_t helper_fmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
> + uint64_t frs3)
> +{
> + return float32_muladd(frs1, frs2, frs3 ^ (uint32_t)INT32_MIN, 0,
> + &env->fp_status);
Missing the requested change to use float32_chs or float_muladd_negate_product
et al throughout the fma family of helpers.
Probably float_muladd_* since you've re-enabled default_nan_mode.
r~
- [Qemu-devel] [PATCH v4 02/22] RISC-V ELF Machine Definition, (continued)
[Qemu-devel] [PATCH v4 06/22] RISC-V FPU Support, Michael Clark, 2018/02/05
- Re: [Qemu-devel] [PATCH v4 06/22] RISC-V FPU Support,
Richard Henderson <=
[Qemu-devel] [PATCH v4 07/22] RISC-V GDB Stub, Michael Clark, 2018/02/05
[Qemu-devel] [PATCH v4 05/22] RISC-V CPU Helpers, Michael Clark, 2018/02/05
[Qemu-devel] [PATCH v4 04/22] RISC-V Disassembler, Michael Clark, 2018/02/05
[Qemu-devel] [PATCH v4 09/22] RISC-V Physical Memory Protection, Michael Clark, 2018/02/05
[Qemu-devel] [PATCH v4 10/22] RISC-V Linux User Emulation, Michael Clark, 2018/02/05
[Qemu-devel] [PATCH v4 08/22] RISC-V TCG Code Generation, Michael Clark, 2018/02/05