Re: [Qemu-devel] [PATCH v6 5/5] target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support

[Ard Biesheuvel]

On 7 February 2018 at 11:49, Alex Bennée <address@hidden> wrote:
>
> Ard Biesheuvel <address@hidden> writes:
>
>> Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to
>> AArch64 user mode emulation.
>
> Are you aware of any processors with ARMv8.2 available yet? It might be
> nice to have a more recent model for system emulation and the pieces
> seems to be coming together.
>

I think Peter's idea was to have so kind of 'max' cpu type that
enables all optional extensions in system emulation mode.
AFAIK none of the Cortex-Axx cores that are public are available with
these crypto features.

>>
>> Signed-off-by: Ard Biesheuvel <address@hidden>
>> ---
>>  linux-user/elfload.c | 19 +++++++++++++++++++
>>  target/arm/cpu64.c   |  4 ++++
>>  2 files changed, 23 insertions(+)
>>
>> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
>> index 20f3d8c2c373..7922ab8eab79 100644
>> --- a/linux-user/elfload.c
>> +++ b/linux-user/elfload.c
>> @@ -512,6 +512,21 @@ enum {
>>      ARM_HWCAP_A64_SHA1          = 1 << 5,
>>      ARM_HWCAP_A64_SHA2          = 1 << 6,
>>      ARM_HWCAP_A64_CRC32         = 1 << 7,
>> +    ARM_HWCAP_A64_ATOMICS       = 1 << 8,
>> +    ARM_HWCAP_A64_FPHP          = 1 << 9,
>> +    ARM_HWCAP_A64_ASIMDHP       = 1 << 10,
>> +    ARM_HWCAP_A64_CPUID         = 1 << 11,
>> +    ARM_HWCAP_A64_ASIMDRDM      = 1 << 12,
>> +    ARM_HWCAP_A64_JSCVT         = 1 << 13,
>> +    ARM_HWCAP_A64_FCMA          = 1 << 14,
>> +    ARM_HWCAP_A64_LRCPC         = 1 << 15,
>> +    ARM_HWCAP_A64_DCPOP         = 1 << 16,
>> +    ARM_HWCAP_A64_SHA3          = 1 << 17,
>> +    ARM_HWCAP_A64_SM3           = 1 << 18,
>> +    ARM_HWCAP_A64_SM4           = 1 << 19,
>> +    ARM_HWCAP_A64_ASIMDDP       = 1 << 20,
>> +    ARM_HWCAP_A64_SHA512        = 1 << 21,
>> +    ARM_HWCAP_A64_SVE           = 1 << 22,
>>  };
>>
>>  #define ELF_HWCAP get_elf_hwcap()
>> @@ -532,6 +547,10 @@ static uint32_t get_elf_hwcap(void)
>>      GET_FEATURE(ARM_FEATURE_V8_SHA1, ARM_HWCAP_A64_SHA1);
>>      GET_FEATURE(ARM_FEATURE_V8_SHA256, ARM_HWCAP_A64_SHA2);
>>      GET_FEATURE(ARM_FEATURE_CRC, ARM_HWCAP_A64_CRC32);
>> +    GET_FEATURE(ARM_FEATURE_V8_SHA3, ARM_HWCAP_A64_SHA3);
>> +    GET_FEATURE(ARM_FEATURE_V8_SM3, ARM_HWCAP_A64_SM3);
>> +    GET_FEATURE(ARM_FEATURE_V8_SM4, ARM_HWCAP_A64_SM4);
>> +    GET_FEATURE(ARM_FEATURE_V8_SHA512, ARM_HWCAP_A64_SHA512);
>>  #undef GET_FEATURE
>>
>>      return hwcaps;
>> diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
>> index 670c07ab6ed4..1c330adc281b 100644
>> --- a/target/arm/cpu64.c
>> +++ b/target/arm/cpu64.c
>> @@ -224,6 +224,10 @@ static void aarch64_any_initfn(Object *obj)
>>      set_feature(&cpu->env, ARM_FEATURE_V8_AES);
>>      set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
>>      set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
>> +    set_feature(&cpu->env, ARM_FEATURE_V8_SHA512);
>> +    set_feature(&cpu->env, ARM_FEATURE_V8_SHA3);
>> +    set_feature(&cpu->env, ARM_FEATURE_V8_SM3);
>> +    set_feature(&cpu->env, ARM_FEATURE_V8_SM4);
>>      set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
>>      set_feature(&cpu->env, ARM_FEATURE_CRC);
>>      cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
>
>
> --
> Alex Bennée