[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v11 07/30] sdhci: add a 'spec_version property' (def
From: |
Philippe Mathieu-Daudé |
Subject: |
[Qemu-devel] [PATCH v11 07/30] sdhci: add a 'spec_version property' (default to v2) |
Date: |
Thu, 8 Feb 2018 13:47:55 -0300 |
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
hw/sd/sdhci-internal.h | 4 ++--
include/hw/sd/sdhci.h | 2 ++
hw/sd/sdhci.c | 27 +++++++++++++++++++++++----
3 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index fc807f08f3..b7751c815f 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -210,9 +210,9 @@
/* Slot interrupt status */
#define SDHC_SLOT_INT_STATUS 0xFC
-/* HWInit Host Controller Version Register 0x0401 */
+/* HWInit Host Controller Version Register */
#define SDHC_HCVER 0xFE
-#define SD_HOST_SPECv2_VERS 0x2401
+#define SDHC_HCVER_VENDOR 0x24
#define SDHC_REGISTERS_MAP_SIZE 0x100
#define SDHC_INSERTION_DELAY (NANOSECONDS_PER_SECOND)
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index 1cf70f8c23..40798aed58 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -77,6 +77,7 @@ typedef struct SDHCIState {
/* Read-only registers */
uint64_t capareg; /* Capabilities Register */
uint64_t maxcurr; /* Maximum Current Capabilities Register */
+ uint16_t version; /* Host Controller Version Register */
uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */
uint32_t buf_maxsz;
@@ -91,6 +92,7 @@ typedef struct SDHCIState {
/* Configurable properties */
bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */
+ uint8_t sd_spec_version;
} SDHCIState;
#define TYPE_PCI_SDHCI "sdhci-pci"
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 817c2525e6..2bcc5ff58a 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -174,7 +174,8 @@ static void sdhci_reset(SDHCIState *s)
timer_del(s->insert_timer);
timer_del(s->transfer_timer);
- /* Set all registers to 0. Capabilities registers are not cleared
+
+ /* Set all registers to 0. Capabilities/Version registers are not cleared
* and assumed to always preserve their value, given to them during
* initialization */
memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg -
(uintptr_t)&s->sdmasysad);
@@ -918,7 +919,7 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset,
unsigned size)
ret = (uint32_t)(s->admasysaddr >> 32);
break;
case SDHC_SLOT_INT_STATUS:
- ret = (SD_HOST_SPECv2_VERS << 16) | sdhci_slotint(s);
+ ret = (s->version << 16) | sdhci_slotint(s);
break;
default:
qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " "
@@ -1174,11 +1175,22 @@ static inline unsigned int sdhci_get_fifolen(SDHCIState
*s)
}
}
+static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp)
+{
+ if (s->sd_spec_version != 2) {
+ error_setg(errp, "Only Spec v2 is supported");
+ return;
+ }
+ s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1);
+}
+
/* --- qdev common --- */
#define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \
- /* Capabilities registers provide information on supported features
- * of this specific host controller implementation */ \
+ DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \
+ \
+ /* Capabilities registers provide information on supported
+ * features of this specific host controller implementation */ \
DEFINE_PROP_UINT64("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \
DEFINE_PROP_UINT64("maxcurr", _state, maxcurr, 0)
@@ -1204,6 +1216,13 @@ static void sdhci_uninitfn(SDHCIState *s)
static void sdhci_common_realize(SDHCIState *s, Error **errp)
{
+ Error *local_err = NULL;
+
+ sdhci_init_readonly_registers(s, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
s->buf_maxsz = sdhci_get_fifolen(s);
s->fifo_buffer = g_malloc0(s->buf_maxsz);
--
2.16.1
- [Qemu-devel] [PATCH v11 00/30] SDHCI: clean v1/2 Specs, UHS-I cards tuning sequence, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 01/30] sdhci: use error_propagate(local_err) in realize(), Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 02/30] sdhci: add qtest to check the SD capabilities register, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 03/30] sdhci: add check_capab_readonly() qtest, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 04/30] sdhci: add a check_capab_baseclock() qtest, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 05/30] sdhci: add a check_capab_sdma() qtest, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 06/30] sdhci: add qtest to check the SD Spec version, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 07/30] sdhci: add a 'spec_version property' (default to v2),
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v11 09/30] sdhci: simplify sdhci_get_fifolen(), Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 08/30] sdhci: use a numeric value for the default CAPAB register, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 10/30] sdhci: check the Spec v1 capabilities correctness, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 12/30] sdhci: Fix 64-bit ADMA2, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 13/30] sdhci: check Spec v2 capabilities (DMA and 64-bit bus), Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 14/30] hw/arm/exynos4210: access the 64-bit capareg with qdev_prop_set_uint64(), Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 15/30] hw/arm/exynos4210: add a comment about a very similar SDHCI (Spec. v2), Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 16/30] hw/arm/xilinx_zynq: fix the capabilities register to match the datasheet, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 18/30] sdhci: rename the hostctl1 register, Philippe Mathieu-Daudé, 2018/02/08
- [Qemu-devel] [PATCH v11 19/30] sdhci: implement the Host Control 2 register (tuning sequence), Philippe Mathieu-Daudé, 2018/02/08