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[Qemu-devel] [PATCH v12 30/30] sdhci: add Spec v4.2 register definitions
From: |
Philippe Mathieu-Daudé |
Subject: |
[Qemu-devel] [PATCH v12 30/30] sdhci: add Spec v4.2 register definitions |
Date: |
Fri, 9 Feb 2018 11:54:30 -0300 |
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
---
hw/sd/sdhci-internal.h | 9 +++++++++
hw/sd/sdhci.c | 14 ++++++++++++++
2 files changed, 23 insertions(+)
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index 0092627076..e1bb733aed 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -198,6 +198,10 @@ FIELD(SDHC_HOSTCTL2, V18_ENA, 3, 1); /* UHS-I
only */
FIELD(SDHC_HOSTCTL2, DRIVER_STRENGTH, 4, 2); /* UHS-I only */
FIELD(SDHC_HOSTCTL2, EXECUTE_TUNING, 6, 1); /* UHS-I only */
FIELD(SDHC_HOSTCTL2, SAMPLING_CLKSEL, 7, 1); /* UHS-I only */
+FIELD(SDHC_HOSTCTL2, UHS_II_ENA, 8, 1); /* since v4 */
+FIELD(SDHC_HOSTCTL2, ADMA2_LENGTH, 10, 1); /* since v4 */
+FIELD(SDHC_HOSTCTL2, CMD23_ENA, 11, 1); /* since v4 */
+FIELD(SDHC_HOSTCTL2, VERSION4, 12, 1); /* since v4 */
FIELD(SDHC_HOSTCTL2, ASYNC_INT, 14, 1);
FIELD(SDHC_HOSTCTL2, PRESET_ENA, 15, 1);
@@ -216,10 +220,12 @@ FIELD(SDHC_CAPAB, SUSPRESUME, 23, 1);
FIELD(SDHC_CAPAB, V33, 24, 1);
FIELD(SDHC_CAPAB, V30, 25, 1);
FIELD(SDHC_CAPAB, V18, 26, 1);
+FIELD(SDHC_CAPAB, BUS64BIT_V4, 27, 1); /* since v4.10 */
FIELD(SDHC_CAPAB, BUS64BIT, 28, 1); /* since v2 */
FIELD(SDHC_CAPAB, ASYNC_INT, 29, 1); /* since v3 */
FIELD(SDHC_CAPAB, SLOT_TYPE, 30, 2); /* since v3 */
FIELD(SDHC_CAPAB, BUS_SPEED, 32, 3); /* since v3 */
+FIELD(SDHC_CAPAB, UHS_II, 35, 8); /* since v4.20 */
FIELD(SDHC_CAPAB, DRIVER_STRENGTH, 36, 3); /* since v3 */
FIELD(SDHC_CAPAB, DRIVER_TYPE_A, 36, 1); /* since v3 */
FIELD(SDHC_CAPAB, DRIVER_TYPE_C, 37, 1); /* since v3 */
@@ -228,12 +234,15 @@ FIELD(SDHC_CAPAB, TIMER_RETUNING, 40, 4); /* since v3
*/
FIELD(SDHC_CAPAB, SDR50_TUNING, 45, 1); /* since v3 */
FIELD(SDHC_CAPAB, RETUNING_MODE, 46, 2); /* since v3 */
FIELD(SDHC_CAPAB, CLOCK_MULT, 48, 8); /* since v3 */
+FIELD(SDHC_CAPAB, ADMA3, 59, 1); /* since v4.20 */
+FIELD(SDHC_CAPAB, V18_VDD2, 60, 1); /* since v4.20 */
/* HWInit Maximum Current Capabilities Register 0x0 */
#define SDHC_MAXCURR 0x48
FIELD(SDHC_MAXCURR, V33_VDD1, 0, 8);
FIELD(SDHC_MAXCURR, V30_VDD1, 8, 8);
FIELD(SDHC_MAXCURR, V18_VDD1, 16, 8);
+FIELD(SDHC_MAXCURR, V18_VDD2, 32, 8); /* since v4.20 */
/* W Force Event Auto CMD12 Error Interrupt Register 0x0000 */
#define SDHC_FEAER 0x50
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 6e5bea804c..c2e4b7003d 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -92,6 +92,20 @@ static void sdhci_check_capareg(SDHCIState *s, Error **errp)
bool unit_mhz;
switch (s->sd_spec_version) {
+ case 4:
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4);
+ msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0);
+ trace_sdhci_capareg("64-bit system bus (v4)", val);
+
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II);
+ msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0);
+ trace_sdhci_capareg("UHS-II", val);
+
+ val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3);
+ msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0);
+ trace_sdhci_capareg("ADMA3", val);
+
+ /* fallback */
case 3:
val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT);
trace_sdhci_capareg("async interrupt", val);
--
2.16.1
- [Qemu-devel] [PATCH v12 19/30] sdhci: implement the Host Control 2 register (tuning sequence), (continued)
- [Qemu-devel] [PATCH v12 19/30] sdhci: implement the Host Control 2 register (tuning sequence), Philippe Mathieu-Daudé, 2018/02/09
- [Qemu-devel] [PATCH v12 20/30] sdbus: add trace events, Philippe Mathieu-Daudé, 2018/02/09
- [Qemu-devel] [PATCH v12 21/30] sdhci: implement UHS-I voltage switch, Philippe Mathieu-Daudé, 2018/02/09
- [Qemu-devel] [PATCH v12 22/30] sdhci: implement CMD/DAT[] fields in the Present State register, Philippe Mathieu-Daudé, 2018/02/09
- [Qemu-devel] [PATCH v12 23/30] hw/arm/bcm2835_peripherals: implement SDHCI Spec v3, Philippe Mathieu-Daudé, 2018/02/09
- [Qemu-devel] [PATCH v12 24/30] hw/arm/bcm2835_peripherals: change maximum block size to 1kB, Philippe Mathieu-Daudé, 2018/02/09
- [Qemu-devel] [PATCH v12 25/30] hw/arm/fsl-imx6: implement SDHCI Spec. v3, Philippe Mathieu-Daudé, 2018/02/09
- [Qemu-devel] [PATCH v12 26/30] hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet, Philippe Mathieu-Daudé, 2018/02/09
- [Qemu-devel] [PATCH v12 28/30] sdhci: check Spec v3 capabilities qtest, Philippe Mathieu-Daudé, 2018/02/09
- [Qemu-devel] [PATCH v12 27/30] hw/arm/xilinx_zynqmp: enable the UHS-I mode, Philippe Mathieu-Daudé, 2018/02/09
- [Qemu-devel] [PATCH v12 30/30] sdhci: add Spec v4.2 register definitions,
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v12 29/30] sdhci: add a check_capab_v3() qtest, Philippe Mathieu-Daudé, 2018/02/09
- Re: [Qemu-devel] [PATCH v12 00/30] SDHCI: clean v1/2 Specs, UHS-I cards tuning sequence, Fam Zheng, 2018/02/12
- Message not available