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[Qemu-devel] [PULL 32/48] sdhci: implement the Host Control 2 register (
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PULL 32/48] sdhci: implement the Host Control 2 register (tuning sequence) |
Date: |
Tue, 13 Feb 2018 13:00:36 +0100 |
From: Philippe Mathieu-Daudé <address@hidden>
[based on a patch from Alistair Francis <address@hidden>
from qemu/xilinx tag xilinx-v2015.2]
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-Id: <address@hidden>
---
hw/sd/sdhci-internal.h | 10 ++++++++++
hw/sd/sdhci.c | 22 +++++++++++++++++++---
include/hw/sd/sdhci.h | 1 +
3 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index 9ab1a71..b3f2692 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -188,6 +188,16 @@ FIELD(SDHC_ACMD12ERRSTS, TIMEOUT_ERR, 1, 1);
FIELD(SDHC_ACMD12ERRSTS, CRC_ERR, 2, 1);
FIELD(SDHC_ACMD12ERRSTS, INDEX_ERR, 4, 1);
+/* Host Control Register 2 (since v3) */
+#define SDHC_HOSTCTL2 0x3E
+FIELD(SDHC_HOSTCTL2, UHS_MODE_SEL, 0, 3);
+FIELD(SDHC_HOSTCTL2, V18_ENA, 3, 1); /* UHS-I only */
+FIELD(SDHC_HOSTCTL2, DRIVER_STRENGTH, 4, 2); /* UHS-I only */
+FIELD(SDHC_HOSTCTL2, EXECUTE_TUNING, 6, 1); /* UHS-I only */
+FIELD(SDHC_HOSTCTL2, SAMPLING_CLKSEL, 7, 1); /* UHS-I only */
+FIELD(SDHC_HOSTCTL2, ASYNC_INT, 14, 1);
+FIELD(SDHC_HOSTCTL2, PRESET_ENA, 15, 1);
+
/* HWInit Capabilities Register 0x05E80080 */
#define SDHC_CAPAB 0x40
FIELD(SDHC_CAPAB, TOCLKFREQ, 0, 6);
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 55b3f3a..2712b82 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -408,14 +408,29 @@ static void sdhci_end_transfer(SDHCIState *s)
static void sdhci_read_block_from_card(SDHCIState *s)
{
int index = 0;
+ uint8_t data;
+ const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK;
if ((s->trnmod & SDHC_TRNS_MULTI) &&
(s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) {
return;
}
- for (index = 0; index < (s->blksize & BLOCK_SIZE_MASK); index++) {
- s->fifo_buffer[index] = sdbus_read_data(&s->sdbus);
+ for (index = 0; index < blk_size; index++) {
+ data = sdbus_read_data(&s->sdbus);
+ if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
+ /* Device is not in tunning */
+ s->fifo_buffer[index] = data;
+ }
+ }
+
+ if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) {
+ /* Device is in tunning */
+ s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK;
+ s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK;
+ s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ |
+ SDHC_DATA_INHIBIT);
+ goto read_done;
}
/* New data now available for READ through Buffer Port Register */
@@ -440,6 +455,7 @@ static void sdhci_read_block_from_card(SDHCIState *s)
}
}
+read_done:
sdhci_update_irq(s);
}
@@ -1005,7 +1021,7 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset,
unsigned size)
ret = s->norintsigen | (s->errintsigen << 16);
break;
case SDHC_ACMD12ERRSTS:
- ret = s->acmd12errsts;
+ ret = s->acmd12errsts | (s->hostctl2 << 16);
break;
case SDHC_CAPAB:
ret = (uint32_t)s->capareg;
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index 5459484..fd606e9 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -73,6 +73,7 @@ typedef struct SDHCIState {
uint16_t norintsigen; /* Normal Interrupt Signal Enable Register */
uint16_t errintsigen; /* Error Interrupt Signal Enable Register */
uint16_t acmd12errsts; /* Auto CMD12 error status register */
+ uint16_t hostctl2; /* Host Control 2 */
uint64_t admasysaddr; /* ADMA System Address Register */
/* Read-only registers */
--
1.8.3.1
- [Qemu-devel] [PULL 15/48] sdhci: add qtest to check the SD capabilities register, (continued)
- [Qemu-devel] [PULL 15/48] sdhci: add qtest to check the SD capabilities register, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 23/48] sdhci: check the Spec v1 capabilities correctness, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 27/48] hw/arm/exynos4210: access the 64-bit capareg with qdev_prop_set_uint64(), Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 20/48] sdhci: add a 'spec_version property' (default to v2), Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 21/48] sdhci: use a numeric value for the default CAPAB register, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 22/48] sdhci: simplify sdhci_get_fifolen(), Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 28/48] hw/arm/exynos4210: add a comment about a very similar SDHCI (Spec. v2), Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 36/48] hw/arm/bcm2835_peripherals: implement SDHCI Spec v3, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 12/48] build-sys: remove useless extra*flags variables, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 19/48] sdhci: add qtest to check the SD Spec version, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 32/48] sdhci: implement the Host Control 2 register (tuning sequence),
Paolo Bonzini <=
- [Qemu-devel] [PULL 25/48] sdhci: Fix 64-bit ADMA2, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 34/48] sdhci: implement UHS-I voltage switch, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 35/48] sdhci: implement CMD/DAT[] fields in the Present State register, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 33/48] sdbus: add trace events, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 29/48] hw/arm/xilinx_zynq: fix the capabilities register to match the datasheet, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 31/48] sdhci: rename the hostctl1 register, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 40/48] hw/arm/xilinx_zynqmp: enable the UHS-I mode, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 37/48] hw/arm/bcm2835_peripherals: change maximum block size to 1kB, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 38/48] hw/arm/fsl-imx6: implement SDHCI Spec. v3, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 39/48] hw/arm/xilinx_zynqmp: fix the capabilities/spec version to match the datasheet, Paolo Bonzini, 2018/02/13