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Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation
From: |
Emilio G. Cota |
Subject: |
Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation |
Date: |
Tue, 13 Feb 2018 16:57:04 -0500 |
User-agent: |
Mutt/1.5.24 (2015-08-30) |
On Thu, Feb 08, 2018 at 14:28:34 +1300, Michael Clark wrote:
> TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
> RISC-V code generator has complete coverage for the Base ISA v2.2,
> Privileged ISA v1.9.1 and Privileged ISA v1.10:
>
> - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10
>
> Reviewed-by: Richard Henderson <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
> ---
(snip)
> +++ b/target/riscv/translate.c
(snip)
> + /* Address comparion failure. However, we still need to
> + provide the memory barrier implied by AQ/RL. */
s/comparion/comparison/
E.
- [Qemu-devel] [PATCH v5 11/23] RISC-V Linux User Emulation, (continued)
- [Qemu-devel] [PATCH v5 11/23] RISC-V Linux User Emulation, Michael Clark, 2018/02/07
- [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation, Michael Clark, 2018/02/07
- Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation, Emilio G. Cota, 2018/02/13
- Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation, Richard Henderson, 2018/02/13
- Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation, Emilio G. Cota, 2018/02/13
- Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation, Richard Henderson, 2018/02/14
- Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation, Emilio G. Cota, 2018/02/14
- Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation, Richard Henderson, 2018/02/14
- Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation, Emilio G. Cota, 2018/02/14
Re: [Qemu-devel] [PATCH v5 09/23] RISC-V TCG Code Generation,
Emilio G. Cota <=
[Qemu-devel] [PATCH v5 13/23] RISC-V HART Array, Michael Clark, 2018/02/07
[Qemu-devel] [PATCH v5 12/23] RISC-V HTIF Console, Michael Clark, 2018/02/07
[Qemu-devel] [PATCH v5 14/23] SiFive RISC-V CLINT Block, Michael Clark, 2018/02/07
[Qemu-devel] [PATCH v5 15/23] SiFive RISC-V PLIC Block, Michael Clark, 2018/02/07