Re: [Qemu-devel] [Qemu-arm] [PATCH v2 10/67] target/arm: Implement SVE Integer Reduction Group

[Peter Maydell]

On 17 February 2018 at 18:22, Richard Henderson
<address@hidden> wrote:
> Excepting MOVPRFX, which isn't a reduction.  Presumably it is
> placed within the group because of its encoding.
>
> Signed-off-by: Richard Henderson <address@hidden>


> @@ -306,8 +399,6 @@ DO_ZPZZ_D(sve_udiv_zpzz_d, uint64_t, DO_DIV)
>  #undef DO_ABD
>  #undef DO_MUL
>  #undef DO_DIV
> -#undef DO_ZPZZ
> -#undef DO_ZPZZ_D
>
>  /* Similar to the ARM LastActiveElement pseudocode function, except the
>     result is multiplied by the element size.  This includes the not found

Hunk in wrong patch or incorrect?

> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
> index 116002792a..49251a53c1 100644
> --- a/target/arm/translate-sve.c
> +++ b/target/arm/translate-sve.c
> @@ -276,6 +276,71 @@ void trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a, 
> uint32_t insn)
>
>  #undef DO_ZPZZ
>
> +/*
> + *** SVE Integer Reduction Group
> + */
> +
> +typedef void gen_helper_gvec_reduc(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_i32);
> +static void do_vpz_ool(DisasContext *s, arg_rpr_esz *a,
> +                       gen_helper_gvec_reduc *fn)
> +{
> +    unsigned vsz = vec_full_reg_size(s);
> +    TCGv_ptr t_zn, t_pg;
> +    TCGv_i32 desc;
> +    TCGv_i64 temp;
> +
> +    if (fn == 0) {
> +        unallocated_encoding(s);
> +        return;
> +    }

Same remarks as for patch 9 about this being too late to
catch unallocated_encodings (or alternatively needing to
do the sve/fp check after this). I won't bother to mention
this issue for later patches, but you can assume it as a
general caveat to my reviewed-by tags.

Otherwise
Reviewed-by: Peter Maydell <address@hidden>

thanks
-- PMM