[Qemu-devel] QEMU Status Update

[Michael Clark]

Hi Folks,

Just a quick update regarding the process of submitting the RISC-V QEMU port 
upstream for inclusion in the QEMU 2.12 release this coming April.

We’ve just submitted our first pull request after receiving positive feedback 
from the v6 patch series submitted last week. We recently contacted 
contributors in response to feedback from Red Hat, to relicense the code as 
GPLv2+ which is the main change in this most recent v7 patch series:

- http://lists.nongnu.org/archive/html/qemu-devel/2018-02/msg06489.html
- http://lists.nongnu.org/archive/html/qemu-devel/2018-02/msg05778.html
- http://lists.nongnu.org/archive/html/qemu-devel/2018-02/msg06132.html

I’d also like to take this opportunity to point out the riscv-qemu wiki where 
we have moved some of the documentation for the port:

- https://github.com/riscv/riscv-qemu/wiki

We no longer have a custom README.md in the repo given the code-base is now 
based on upstream QEMU. I’ve added wiki links to SiFive’s freedom-u-sdk which 
creates build recipes to create qemu and a bootable buildroot-based linux image 
that will run on the freedom U series VC707 FPGA, SiFive’s new HiFive Unleashed 
board and of course riscv-qemu. I’ve also added links to the Fedora RISC-V 
Architecture page and the Debian RISC-V Architecture page which have additional 
links to RISC-V Linux packages and root images.

With the current version of riscv-qemu we are able to run Privileged ISA v1.9.1 
riscv-linux/bbl, on the spike_v1.9.1 machine, Privileged ISA v1.10 
riscv-linux/bbl on the spike_v1.10 and virt machines, HiFive1 binaries on the 
sifive_e300 machine and we have working MTTCG-enabled SMP on the virt machine 
thanks to work done by Stefan O’Rear and Richard Henderson on thread-safe 
atomics.

There is still a lot of future development work that we can switch our 
attention to once the port is upstream. This is a non-exhaustive list, just to 
give you an idea of future work that needs to be done:

- Allow on-the-fly ‘misa’ changes, perhaps with translation cache flushing
        - Currently the misa flag is read-only
- Support the rules being discussed for enabling and disabling misa C flag
        - Currently QEMU allows instruction fetches on half-word (16-bit) 
boundaries when C is disabled
- Disable MMU when misa S flag is not set
        - Currently QEMU allows configuring of the MMU on the E-series machine
        - This works because E-series code does not touch the satp register
- Add vendor specific cpu models such as ’sifive-e31’, ’sifive-e51’, 
’sifive-u54’, etc
        - Currently we have ‘generic-imacs’, ‘generic-imafdcsu’, etc
- Improve device support
        - FIFO and interrupt mode support for the SiFive UART along with Linux 
driver
        - PCI host (GPEX) for the ‘virt’ machine to enable virtio-pci
        - SPI and GPIO devices for the SiFive boards
        - Add generic GPIO based power-off and reset
        - Implement HTIF queuing and fix 32-bit support
- Privileged ISA v1.10 and v1.11
        - Add support for TSR, TW and TVM flags (priv v1.10)
        - Add Hypervisor support (draft priv v1.11)

Thanks to everyone who helped with patch review, testing, patches and pull 
requests. I’d also like to give special thanks to Sagar who did a huge amount 
of the original work on the port. 

Note: I’m explicitly cross-posting as this email is relevant to both the RISC-V 
software development community and the QEMU development community.

Regards,
Michael.