Re: [Qemu-devel] [Qemu-arm] [PATCH v3 14/16] target/arm: Decode aa32 armv8.3 2-reg-index

[Peter Maydell]

On 28 February 2018 at 19:31, Richard Henderson
<address@hidden> wrote:
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  target/arm/translate.c | 61 
> ++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 61 insertions(+)
>

> @@ -8492,6 +8547,12 @@ static void disas_arm_insn(DisasContext *s, unsigned 
> int insn)
>                  goto illegal_op;
>              }
>              return;
> +        } else if ((insn & 0x0f000a00) == 0x0e000800
> +                   && arm_dc_feature(s, ARM_FEATURE_V8)) {
> +            if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
> +                goto illegal_op;
> +            }
> +            return;
>          } else if ((insn & 0x0fe00000) == 0x0c400000) {
>              /* Coprocessor double register transfer.  */
>              ARCH(5TE);

Missing the similar code for disas_thumb2_insn() again.

Otherwise
Reviewed-by: Peter Maydell <address@hidden>

thanks
-- PMM