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Re: [Qemu-devel] [PULL 00/42] target-arm queue
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From: |
Peter Maydell |
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Subject: |
Re: [Qemu-devel] [PULL 00/42] target-arm queue |
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Date: |
Thu, 1 Mar 2018 14:45:19 +0000 |
On 1 March 2018 at 13:00, <address@hidden> wrote:
> Hi,
>
> This series seems to have some coding style problems. See output below for
> more information:
>
> Type: series
> Message-id: address@hidden
> Subject: [Qemu-devel] [PULL 00/42] target-arm queue
Fam -- any idea why patchew sent two checkpatch-issues emails for
this patchset ? The Message-IDs are:
<address@hidden>
<address@hidden>
thanks
-- PMM
- [Qemu-devel] [PULL 33/42] arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16, (continued)
- [Qemu-devel] [PULL 33/42] arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 36/42] arm/translate-a64: add FP16 FMOV to simd_mod_imm, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 34/42] arm/helper.c: re-factor rsqrte and add rsqrte_f16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 38/42] arm/translate-a64: implement simd_scalar_three_reg_same_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 41/42] linux-user: Report AArch64 FP16 support via hwcap bits, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 42/42] MAINTAINERS: Update my email address, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 37/42] arm/translate-a64: add all FP16 ops in simd_scalar_pairwise, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 39/42] arm/translate-a64: add all single op FP16 to handle_fp_1src_half, Peter Maydell, 2018/03/01
- Re: [Qemu-devel] [PULL 00/42] target-arm queue, no-reply, 2018/03/01
- Re: [Qemu-devel] [PULL 00/42] target-arm queue, no-reply, 2018/03/01
- Re: [Qemu-devel] [PULL 00/42] target-arm queue,
Peter Maydell <=
- Re: [Qemu-devel] [PULL 00/42] target-arm queue, Peter Maydell, 2018/03/01