Re: [Qemu-devel] [PATCH v1 09/22] RISC-V: Include hexidecimal instruction in

[Michael Clark]

On Wed, Mar 7, 2018 at 12:09 PM, Philippe Mathieu-Daudé <address@hidden>
wrote:

> On 03/06/2018 05:43 PM, Michael Clark wrote:
> > This was added to help debug issues using -d in_asm. It is
> > useful to see the instruction bytes, as one can detect if
> > one is trying to execute ASCII or device-tree magic.
>
> clean :)


Yap. One feature crept in. I was trying to debug early firmware (to
separate firmware and kernel image) and this helped me discover that I was
jumping into device tree. 0xfeedd00d is the device-tree magic and it is
actually valid RVC code so I was quite puzzled until I modifed the
disassembler to show the instruction bytes.

> Signed-off-by: Michael Clark <address@hidden>
> > Signed-off-by: Palmer Dabbelt <address@hidden>
>
> Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
>
> > ---
> >  disas/riscv.c | 39 ++++++++++++++++++++-------------------
> >  1 file changed, 20 insertions(+), 19 deletions(-)
> >
> > diff --git a/disas/riscv.c b/disas/riscv.c
> > index 3c17501..4580308 100644
> > --- a/disas/riscv.c
> > +++ b/disas/riscv.c
> > @@ -2769,25 +2769,6 @@ static void format_inst(char *buf, size_t buflen,
> size_t tab, rv_decode *dec)
> >      char tmp[64];
> >      const char *fmt;
> >
> > -    if (dec->op == rv_op_illegal) {
> > -        size_t len = inst_length(dec->inst);
> > -        switch (len) {
> > -        case 2:
> > -            snprintf(buf, buflen, "(0x%04" PRIx64 ")", dec->inst);
> > -            break;
> > -        case 4:
> > -            snprintf(buf, buflen, "(0x%08" PRIx64 ")", dec->inst);
> > -            break;
> > -        case 6:
> > -            snprintf(buf, buflen, "(0x%012" PRIx64 ")", dec->inst);
> > -            break;
> > -        default:
> > -            snprintf(buf, buflen, "(0x%016" PRIx64 ")", dec->inst);
> > -            break;
> > -        }
> > -        return;
> > -    }
> > -
> >      fmt = opcode_data[dec->op].format;
> >      while (*fmt) {
> >          switch (*fmt) {
> > @@ -3004,6 +2985,11 @@ disasm_inst(char *buf, size_t buflen, rv_isa isa,
> uint64_t pc, rv_inst inst)
> >      format_inst(buf, buflen, 16, &dec);
> >  }
> >
> > +#define INST_FMT_2 "%04" PRIx64 "              "
> > +#define INST_FMT_4 "%08" PRIx64 "          "
> > +#define INST_FMT_6 "%012" PRIx64 "      "
> > +#define INST_FMT_8 "%016" PRIx64 "  "
> > +
> >  static int
> >  print_insn_riscv(bfd_vma memaddr, struct disassemble_info *info, rv_isa
> isa)
> >  {
> > @@ -3031,6 +3017,21 @@ print_insn_riscv(bfd_vma memaddr, struct
> disassemble_info *info, rv_isa isa)
> >          }
> >      }
> >
> > +    switch (len) {
> > +    case 2:
> > +        (*info->fprintf_func)(info->stream, INST_FMT_2, inst);
> > +        break;
> > +    case 4:
> > +        (*info->fprintf_func)(info->stream, INST_FMT_4, inst);
> > +        break;
> > +    case 6:
> > +        (*info->fprintf_func)(info->stream, INST_FMT_6, inst);
> > +        break;
> > +    default:
> > +        (*info->fprintf_func)(info->stream, INST_FMT_8, inst);
> > +        break;
> > +    }
> > +
> >      disasm_inst(buf, sizeof(buf), isa, memaddr, inst);
> >      (*info->fprintf_func)(info->stream, "%s", buf);
> >
> >
>