On Fri, 9 Mar 2018 at 12:18 AM, Michael Clark <address@hidden> wrote:
On Fri, 9 Mar 2018 at 12:10 AM, Michael Clark <address@hidden> wrote:
On Thu, 8 Mar 2018 at 11:02 PM, Peter Maydell <address@hidden>
wrote:
On 6 March 2018 at 19:46, Michael Clark <address@hidden> wrote:
You are making this very hard. Do you work for Arm perchance? I really
wouldn’t be surprised if our port is being sandbagged by Arm. Apologies for
being so direct about this, but things like this happen...
I have complied with practically every review request and the sign-offs
are there. It’s a bit ridiculous.
It would be nice to find someone neutral, unrelated to Arm, to merge our PR
Some history on the origins of RISC to put things in perspective:
https://en.m.wikipedia.org/wiki/Berkeley_RISC
David Patterson worked with Andrew Waterman and Krste Asanovic on the
design of RISC-V. Sagar did most of the work on the QEMU port and he
agreeded to sign off on all patches. The SiFive patches only have sign-offs
from SiFive because SiFive was the sole contributor for its hardware model,
beside the SiFiveUART which has Stefan’s sign-off.
In any case it seems there is not enough review bandwidth in the QEMU
project as a whole and the policy to accept contributions is too strict to
be reasonable, given earnest attempts to comply with *all* review feedback.
Not impressed.