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Re: [Qemu-devel] [PATCH v2 13/23] RISC-V: Make some header guards more s
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [PATCH v2 13/23] RISC-V: Make some header guards more specific |
Date: |
Sat, 10 Mar 2018 21:30:38 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 |
On 03/09/2018 05:12 AM, Michael Clark wrote:
> Cc: Sagar Karandikar <address@hidden>
> Cc: Bastian Koppelmann <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
> Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> ---
> include/hw/riscv/spike.h | 4 ++--
> include/hw/riscv/virt.h | 4 ++--
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h
> index 8410430..641b70d 100644
> --- a/include/hw/riscv/spike.h
> +++ b/include/hw/riscv/spike.h
> @@ -16,8 +16,8 @@
> * this program. If not, see <http://www.gnu.org/licenses/>.
> */
>
> -#ifndef HW_SPIKE_H
> -#define HW_SPIKE_H
> +#ifndef HW_RISCV_SPIKE_H
> +#define HW_RISCV_SPIKE_H
>
> typedef struct {
> /*< private >*/
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index b91a412..3a4f23e 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -16,8 +16,8 @@
> * this program. If not, see <http://www.gnu.org/licenses/>.
> */
>
> -#ifndef HW_VIRT_H
> -#define HW_VIRT_H
> +#ifndef HW_RISCV_VIRT_H
> +#define HW_RISCV_VIRT_H
>
> typedef struct {
> /*< private >*/
>
- [Qemu-devel] [PATCH v2 07/23] RISC-V: Remove unused class definitions, (continued)
- [Qemu-devel] [PATCH v2 07/23] RISC-V: Remove unused class definitions, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 08/23] RISC-V: Make sure rom has space for fdt, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 09/23] RISC-V: Include intruction hex in disassembly, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 10/23] RISC-V: Hold rcu_read_lock when accessing memory, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 11/23] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 12/23] RISC-V: Update E order and I extension order, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 14/23] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 13/23] RISC-V: Make some header guards more specific, Michael Clark, 2018/03/08
- Re: [Qemu-devel] [PATCH v2 13/23] RISC-V: Make some header guards more specific,
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v2 16/23] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 15/23] RISC-V: Use memory_region_is_ram in pte update, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 17/23] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 18/23] RISC-V: Remove braces from satp case statement, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 19/23] RISC-V: riscv-qemu port supports sv39 and sv48, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 20/23] RISC-V: vectored traps are optional, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 21/23] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/03/08
- [Qemu-devel] [PATCH v2 22/23] RISC-V: Remove support for adhoc X_COP interrupt, Michael Clark, 2018/03/08