[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v3 06/22] target/arm: Mask PMU register writes based
From: |
Aaron Lindsay |
Subject: |
[Qemu-devel] [PATCH v3 06/22] target/arm: Mask PMU register writes based on PMCR_EL0.N |
Date: |
Fri, 16 Mar 2018 16:31:04 -0400 |
This is in preparation for enabling counters other than PMCCNTR
Signed-off-by: Aaron Lindsay <address@hidden>
---
target/arm/helper.c | 24 +++++++++++++++---------
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 6480b80..5d5c738 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -52,11 +52,6 @@ typedef struct V8M_SAttributes {
static void v8m_security_lookup(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
V8M_SAttributes *sattrs);
-
-/* Definitions for the PMCCNTR and PMCR registers */
-#define PMCRD 0x8
-#define PMCRC 0x4
-#define PMCRE 0x1
#endif
static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
@@ -906,6 +901,17 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
REGINFO_SENTINEL
};
+/* Definitions for the PMU registers */
+#define PMCRN_MASK 0xf800
+#define PMCRN_SHIFT 11
+#define PMCRD 0x8
+#define PMCRC 0x4
+#define PMCRE 0x1
+
+#define PMU_NUM_COUNTERS(env) ((env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT)
+/* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */
+#define PMU_COUNTER_MASK(env) ((1 << 31) | ((1 << PMU_NUM_COUNTERS(env)) - 1))
+
static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
@@ -1124,14 +1130,14 @@ static void pmccfiltr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- value &= (1 << 31);
+ value &= PMU_COUNTER_MASK(env);
env->cp15.c9_pmcnten |= value;
}
static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- value &= (1 << 31);
+ value &= PMU_COUNTER_MASK(env);
env->cp15.c9_pmcnten &= ~value;
}
@@ -1179,14 +1185,14 @@ static void pmintenset_write(CPUARMState *env, const
ARMCPRegInfo *ri,
uint64_t value)
{
/* We have no event counters so only the C bit can be changed */
- value &= (1 << 31);
+ value &= PMU_COUNTER_MASK(env);
env->cp15.c9_pminten |= value;
}
static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
- value &= (1 << 31);
+ value &= PMU_COUNTER_MASK(env);
env->cp15.c9_pminten &= ~value;
}
--
Qualcomm Datacenter Technologies as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
- [Qemu-devel] [PATCH v3 00/22] More fully implement ARM PMUv3, Aaron Lindsay, 2018/03/16
- [Qemu-devel] [PATCH v3 02/22] target/arm: A15 PMCEID0 initialization style nit, Aaron Lindsay, 2018/03/16
- [Qemu-devel] [PATCH v3 03/22] target/arm: Check PMCNTEN for whether PMCCNTR is enabled, Aaron Lindsay, 2018/03/16
- [Qemu-devel] [PATCH v3 05/22] target/arm: Reorganize PMCCNTR read, write, sync, Aaron Lindsay, 2018/03/16
- [Qemu-devel] [PATCH v3 04/22] target/arm: Treat PMCCNTR as alias of PMCCNTR_EL0, Aaron Lindsay, 2018/03/16
- [Qemu-devel] [PATCH v3 06/22] target/arm: Mask PMU register writes based on PMCR_EL0.N,
Aaron Lindsay <=
- [Qemu-devel] [PATCH v3 08/22] target/arm: Support multiple EL change hooks, Aaron Lindsay, 2018/03/16
[Qemu-devel] [PATCH v3 07/22] target/arm: Fetch GICv3 state directly from CPUARMState, Aaron Lindsay, 2018/03/16
[Qemu-devel] [PATCH v3 09/22] target/arm: Add pre-EL change hooks, Aaron Lindsay, 2018/03/16
[Qemu-devel] [PATCH v3 10/22] target/arm: Allow EL change hooks to do IO, Aaron Lindsay, 2018/03/16
[Qemu-devel] [PATCH v3 14/22] target/arm: Make PMOVSCLR 64 bits wide, Aaron Lindsay, 2018/03/16