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Re: [Qemu-devel] [PATCH v3 23/24] RISC-V: Convert cpu definition towards


From: Igor Mammedov
Subject: Re: [Qemu-devel] [PATCH v3 23/24] RISC-V: Convert cpu definition towards future model
Date: Mon, 19 Mar 2018 16:47:40 +0100

On Fri, 16 Mar 2018 12:41:20 -0700
Michael Clark <address@hidden> wrote:

> - Model borrowed from target/sh4/cpu.c
> - Rewrote riscv_cpu_list to use object_class_get_list
> - Dropped 'struct RISCVCPUInfo' and used TypeInfo array
> - Replaced riscv_cpu_register_types with DEFINE_TYPES
> - Marked base class as abstract
> 
> Cc: Igor Mammedov <address@hidden>
> Cc: Sagar Karandikar <address@hidden>
> Cc: Bastian Koppelmann <address@hidden>
> Signed-off-by: Palmer Dabbelt <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
> Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Igor Mammedov <address@hidden>

> ---
[...]

> -static void riscv_cpu_register_types(void)
> +static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
>  {
> -    const RISCVCPUInfo *info = riscv_cpus;
> +    RISCVCPUListState *s = user_data;
> +    const char *typename = object_class_get_name(OBJECT_CLASS(data));
> +    int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
This also fixes "-cpu" output,
before this patch:

# qemu-system-riscv32 -cpu help 
any-riscv-cpu
rv32gcsu-v1.9.1-riscv-cpu
rv32gcsu-v1.10.0-riscv-cpu
rv32imacu-nommu-riscv-cpu
sifive-e31-riscv-cpu
sifive-u34-riscv-cpu

# qemu-system-riscv32 -cpu rv32gcsu-v1.9.1-riscv-cpu 
qemu-system-riscv32: unable to find CPU model 'rv32gcsu-v1.9.1-riscv-cpu'

after this patch:

# qemu-system-riscv32 -cpu help
any
rv32gcsu-v1.10.0
rv32gcsu-v1.9.1
rv32imacu-nommu
sifive-e31
sifive-u34

which cpu model matches conversion rules of riscv_cpu_class_by_name()
and matching cpu type is found as expected.

> -    type_register_static(&riscv_cpu_type_info);
> +    (*s->cpu_fprintf)(s->file, "%.*s\n", len, typename);
> +}
[...]




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