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[Qemu-devel] [PATCH v4 14/26] RISC-V: Make virt header comment title con
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v4 14/26] RISC-V: Make virt header comment title consistent |
Date: |
Mon, 19 Mar 2018 14:18:37 -0700 |
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 3a4f23e..91163d6 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -1,5 +1,5 @@
/*
- * SiFive VirtIO Board
+ * QEMU RISC-V VirtIO machine interface
*
* Copyright (c) 2017 SiFive, Inc.
*
--
2.7.0
- [Qemu-devel] [PATCH v4 02/26] RISC-V: Replace hardcoded constants with enum values, (continued)
- [Qemu-devel] [PATCH v4 02/26] RISC-V: Replace hardcoded constants with enum values, Michael Clark, 2018/03/19
- [Qemu-devel] [PATCH v4 03/26] RISC-V: Make virt board description match spike, Michael Clark, 2018/03/19
- [Qemu-devel] [PATCH v4 10/26] RISC-V: Hold rcu_read_lock when accessing memory, Michael Clark, 2018/03/19
- [Qemu-devel] [PATCH v4 09/26] RISC-V: Include intruction hex in disassembly, Michael Clark, 2018/03/19
- [Qemu-devel] [PATCH v4 07/26] RISC-V: Remove unused class definitions, Michael Clark, 2018/03/19
- [Qemu-devel] [PATCH v4 12/26] RISC-V: Update E order and I extension order, Michael Clark, 2018/03/19
- [Qemu-devel] [PATCH v4 13/26] RISC-V: Make some header guards more specific, Michael Clark, 2018/03/19
- [Qemu-devel] [PATCH v4 16/26] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/03/19
- [Qemu-devel] [PATCH v4 11/26] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/03/19
- [Qemu-devel] [PATCH v4 17/26] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/03/19
- [Qemu-devel] [PATCH v4 14/26] RISC-V: Make virt header comment title consistent,
Michael Clark <=
- [Qemu-devel] [PATCH v4 24/26] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/03/19
- [Qemu-devel] [PATCH v4 21/26] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/03/19
- [Qemu-devel] [PATCH v4 20/26] RISC-V: vectored traps are optional, Michael Clark, 2018/03/19
- [Qemu-devel] [PATCH v4 15/26] RISC-V: Use memory_region_is_ram in pte update, Michael Clark, 2018/03/19
- [Qemu-devel] [PATCH v4 22/26] RISC-V: Remove support for adhoc X_COP interrupt, Michael Clark, 2018/03/19
- [Qemu-devel] [PATCH v4 23/26] RISC-V: Convert cpu definition towards future model, Michael Clark, 2018/03/19
- [Qemu-devel] [PATCH v4 25/26] RISC-V: Remove erroneous comment from translate.c, Michael Clark, 2018/03/19
- [Qemu-devel] [PATCH v4 19/26] RISC-V: riscv-qemu port supports sv39 and sv48, Michael Clark, 2018/03/19
- [Qemu-devel] [PATCH v4 18/26] RISC-V: Remove braces from satp case statement, Michael Clark, 2018/03/19
- [Qemu-devel] [PATCH v4 26/26] RISC-V: Fix riscv_isa_string memory size bug, Michael Clark, 2018/03/19