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Re: [Qemu-devel] [PATCH v3 10/24] RISC-V: Hold rcu_read_lock when access
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v3 10/24] RISC-V: Hold rcu_read_lock when accessing memory |
Date: |
Wed, 21 Mar 2018 16:33:51 +0000 |
On 21 March 2018 at 13:55, Paolo Bonzini <address@hidden> wrote:
> On 19/03/2018 22:07, Michael Clark wrote:
>> We need to use atomic_cmpxchg
>> in the PTE update to detect the case where the PTE has changed between
>> reading it and updating the accessed dirty bits.
>
> Yes, this makes sense. In fact having such a function (more precisely
> address_space_atomic_cmpxchg) would be useful for x86 too. Right now
> x86 is wrong in not using cmpxchg.
Yeah, this is a known missing feature in our APIs for memory
accesses (it only starts to matter with MTTCG, really). We
ought to have functions that guarantee that they do the
access as a single 32/64 bit load/store, as well as
having atomic support. PPC and Arm TLB walk code will need
these. For the moment we just ignore the possibility of
races here, but for the 2.13 timeframe we really ought to
design a solution to this properly.
thanks
-- PMM
- [Qemu-devel] [PATCH v3 02/24] RISC-V: Replace hardcoded constants with enum values, (continued)
- [Qemu-devel] [PATCH v3 02/24] RISC-V: Replace hardcoded constants with enum values, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 05/24] RISC-V: Remove identity_translate from load_elf, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 06/24] RISC-V: Mark ROM read-only after copying in code, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 07/24] RISC-V: Remove unused class definitions, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 08/24] RISC-V: Make sure rom has space for fdt, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 09/24] RISC-V: Include intruction hex in disassembly, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 10/24] RISC-V: Hold rcu_read_lock when accessing memory, Michael Clark, 2018/03/16
[Qemu-devel] [PATCH v3 13/24] RISC-V: Make some header guards more specific, Michael Clark, 2018/03/16
[Qemu-devel] [PATCH v3 12/24] RISC-V: Update E order and I extension order, Michael Clark, 2018/03/16
[Qemu-devel] [PATCH v3 11/24] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/03/16
[Qemu-devel] [PATCH v3 14/24] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/03/16
[Qemu-devel] [PATCH v3 15/24] RISC-V: Use memory_region_is_ram in pte update, Michael Clark, 2018/03/16
[Qemu-devel] [PATCH v3 16/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/03/16
[Qemu-devel] [PATCH v3 18/24] RISC-V: Remove braces from satp case statement, Michael Clark, 2018/03/16
[Qemu-devel] [PATCH v3 17/24] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/03/16
[Qemu-devel] [PATCH v3 19/24] RISC-V: riscv-qemu port supports sv39 and sv48, Michael Clark, 2018/03/16
[Qemu-devel] [PATCH v3 20/24] RISC-V: vectored traps are optional, Michael Clark, 2018/03/16