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[Qemu-devel] [PATCH v1 04/14] fp-test: add muladd variants
From: |
Emilio G. Cota |
Subject: |
[Qemu-devel] [PATCH v1 04/14] fp-test: add muladd variants |
Date: |
Wed, 21 Mar 2018 16:11:39 -0400 |
These are a few muladd-related operations that the original IBM syntax
does not specify; model files for these are in muladd.fptest.
Signed-off-by: Emilio G. Cota <address@hidden>
---
tests/fp-test/fp-test.c | 24 +++++++++++++++++++++
tests/fp-test/muladd.fptest | 51 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 75 insertions(+)
create mode 100644 tests/fp-test/muladd.fptest
diff --git a/tests/fp-test/fp-test.c b/tests/fp-test/fp-test.c
index 27637c4..2200d40 100644
--- a/tests/fp-test/fp-test.c
+++ b/tests/fp-test/fp-test.c
@@ -53,6 +53,9 @@ enum op {
OP_SUB,
OP_MUL,
OP_MULADD,
+ OP_MULADD_NEG_ADDEND,
+ OP_MULADD_NEG_PRODUCT,
+ OP_MULADD_NEG_RESULT,
OP_DIV,
OP_SQRT,
OP_MINNUM,
@@ -69,6 +72,9 @@ static const struct op_desc ops[] = {
[OP_SUB] = { "-", 2 },
[OP_MUL] = { "*", 2 },
[OP_MULADD] = { "*+", 3 },
+ [OP_MULADD_NEG_ADDEND] = { "*+nc", 3 },
+ [OP_MULADD_NEG_PRODUCT] = { "*+np", 3 },
+ [OP_MULADD_NEG_RESULT] = { "*+nr", 3 },
[OP_DIV] = { "/", 2 },
[OP_SQRT] = { "V", 1 },
[OP_MINNUM] = { "<C", 2 },
@@ -463,6 +469,15 @@ static enum error soft_tester(struct test_op *t)
case OP_MULADD:
res = float32_muladd(a, b, c, 0, s);
break;
+ case OP_MULADD_NEG_ADDEND:
+ res = float32_muladd(a, b, c, float_muladd_negate_c, s);
+ break;
+ case OP_MULADD_NEG_PRODUCT:
+ res = float32_muladd(a, b, c, float_muladd_negate_product, s);
+ break;
+ case OP_MULADD_NEG_RESULT:
+ res = float32_muladd(a, b, c, float_muladd_negate_result, s);
+ break;
case OP_DIV:
res = float32_div(a, b, s);
break;
@@ -522,6 +537,15 @@ static enum error soft_tester(struct test_op *t)
case OP_MULADD:
res64 = float64_muladd(a, b, c, 0, s);
break;
+ case OP_MULADD_NEG_ADDEND:
+ res64 = float64_muladd(a, b, c, float_muladd_negate_c, s);
+ break;
+ case OP_MULADD_NEG_PRODUCT:
+ res64 = float64_muladd(a, b, c, float_muladd_negate_product, s);
+ break;
+ case OP_MULADD_NEG_RESULT:
+ res64 = float64_muladd(a, b, c, float_muladd_negate_result, s);
+ break;
case OP_DIV:
res64 = float64_div(a, b, s);
break;
diff --git a/tests/fp-test/muladd.fptest b/tests/fp-test/muladd.fptest
new file mode 100644
index 0000000..6cd48ff
--- /dev/null
+++ b/tests/fp-test/muladd.fptest
@@ -0,0 +1,51 @@
+# nc == negate addend
+b32*+nc =0 -Inf -Inf +Inf -> Q i
+b32*+nc =0 -1.7FFFFFP127 -Inf +Inf -> Q i
+b32*+nc =0 -1.6C9AE7P113 -Inf +Inf -> Q i
+b32*+nc =0 -1.000000P-126 -Inf +Inf -> Q i
+b32*+nc =0 -0.7FFFFFP-126 -Inf +Inf -> Q i
+b32*+nc =0 -0.1B977AP-126 -Inf +Inf -> Q i
+b32*+nc =0 -0.000001P-126 -Inf +Inf -> Q i
+b32*+nc =0 -1.000000P0 -Inf +Inf -> Q i
+b32*+nc =0 -Zero -Inf +Inf -> Q i
+b32*+nc =0 +Zero -Inf +Inf -> Q i
+b32*+nc =0 -Zero -1.000000P-126 +1.7FFFFFP127 -> -1.7FFFFFP127
+b32*+nc =0 +Zero -1.000000P-126 +1.7FFFFFP127 -> -1.7FFFFFP127
+b32*+nc =0 -1.000000P-126 -1.7FFFFFP127 -1.4B9156P109 -> +1.4B9156P109 x
+b32*+nc =0 -0.7FFFFFP-126 -1.7FFFFFP127 -1.51BA59P-113 -> +1.7FFFFDP1 x
+b32*+nc =0 -0.3D6B57P-126 -1.7FFFFFP127 -1.265398P-67 -> +1.75AD5BP0 x
+b32*+nc =0 -0.000001P-126 -1.7FFFFFP127 -1.677330P-113 -> +1.7FFFFFP-22 x
+
+# np == negate product
+b32*+np =0 +Inf -Inf -Inf -> Q i
+b32*+np =0 +1.7FFFFFP127 -Inf -Inf -> Q i
+b32*+np =0 +1.6C9AE7P113 -Inf -Inf -> Q i
+b32*+np =0 +1.000000P-126 -Inf -Inf -> Q i
+b32*+np =0 +0.7FFFFFP-126 -Inf -Inf -> Q i
+b32*+np =0 +0.1B977AP-126 -Inf -Inf -> Q i
+b32*+np =0 +0.000001P-126 -Inf -Inf -> Q i
+b32*+np =0 +1.000000P0 -Inf -Inf -> Q i
+b32*+np =0 +Zero -Inf -Inf -> Q i
+b32*+np =0 +Zero -Inf -Inf -> Q i
+b32*+np =0 -Zero -1.000000P-126 -1.7FFFFFP127 -> -1.7FFFFFP127
+b32*+np =0 +Zero -1.000000P-126 -1.7FFFFFP127 -> -1.7FFFFFP127
+b32*+np =0 -1.3A6A89P-18 +1.24E7AEP9 -0.7FFFFFP-126 -> +1.7029E9P-9 x
+
+# nr == negate result
+b32*+nr =0 -Inf -Inf -Inf -> Q i
+b32*+nr =0 -1.7FFFFFP127 -Inf -Inf -> Q i
+b32*+nr =0 -1.6C9AE7P113 -Inf -Inf -> Q i
+b32*+nr =0 -1.000000P-126 -Inf -Inf -> Q i
+b32*+nr =0 -0.7FFFFFP-126 -Inf -Inf -> Q i
+b32*+nr =0 -0.1B977AP-126 -Inf -Inf -> Q i
+b32*+nr =0 -0.000001P-126 -Inf -Inf -> Q i
+b32*+nr =0 -1.000000P0 -Inf -Inf -> Q i
+b32*+nr =0 -Zero -Inf -Inf -> Q i
+b32*+nr =0 -Zero -Inf -Inf -> Q i
+b32*+nr =0 +Zero -1.000000P-126 -1.7FFFFFP127 -> +1.7FFFFFP127
+b32*+nr =0 -Zero -1.000000P-126 -1.7FFFFFP127 -> +1.7FFFFFP127
+b32*+nr =0 -1.000000P-126 -1.7FFFFFP127 -1.4B9156P109 -> +1.4B9156P109 x
+b32*+nr =0 -0.7FFFFFP-126 -1.7FFFFFP127 -1.51BA59P-113 -> -1.7FFFFDP1 x
+b32*+nr =0 -0.3D6B57P-126 -1.7FFFFFP127 -1.265398P-67 -> -1.75AD5BP0 x
+b32*+nr =0 -0.000001P-126 -1.7FFFFFP127 -1.677330P-113 -> -1.7FFFFFP-22 x
+b32*+nr =0 +1.72E53AP-33 -1.7FFFFFP127 -1.5AA684P-2 -> +1.72E539P95 x
--
2.7.4
- [Qemu-devel] [PATCH v1 05/14] softfloat: add float32_is_normal and float64_is_normal, (continued)
[Qemu-devel] [PATCH v1 04/14] fp-test: add muladd variants,
Emilio G. Cota <=
[Qemu-devel] [PATCH v1 07/14] fpu: introduce hostfloat, Emilio G. Cota, 2018/03/21
Re: [Qemu-devel] [PATCH v1 00/14] fp-test + hostfloat, no-reply, 2018/03/21
Re: [Qemu-devel] [PATCH v1 00/14] fp-test + hostfloat, no-reply, 2018/03/22
Re: [Qemu-devel] [PATCH v1 00/14] fp-test + hostfloat, Alex Bennée, 2018/03/22