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[Qemu-devel] [PULL 03/24] RISC-V: Make virt board description match spik
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PULL 03/24] RISC-V: Make virt board description match spike |
Date: |
Wed, 21 Mar 2018 13:46:39 -0700 |
This makes 'qemu-system-riscv64 -machine help' output more tidy
and consistent.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
---
hw/riscv/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index a402856..0055439 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -404,7 +404,7 @@ static const TypeInfo riscv_virt_board_device = {
static void riscv_virt_board_machine_init(MachineClass *mc)
{
- mc->desc = "RISC-V VirtIO Board (Privileged spec v1.10)";
+ mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)";
mc->init = riscv_virt_board_init;
mc->max_cpus = 8; /* hardcoded limit in BBL */
}
--
2.7.0
- [Qemu-devel] [PULL 00/24] RISC-V: Post-merge spec conformance and cleanup v5, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 04/24] RISC-V: Use ROM base address and size from memmap, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 01/24] RISC-V: Make virt create_fdt interface consistent, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 03/24] RISC-V: Make virt board description match spike,
Michael Clark <=
- [Qemu-devel] [PULL 02/24] RISC-V: Replace hardcoded constants with enum values, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 07/24] RISC-V: Remove unused class definitions, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 06/24] RISC-V: Mark ROM read-only after copying in code, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 05/24] RISC-V: Remove identity_translate from load_elf, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 14/24] RISC-V: Use memory_region_is_ram in pte update, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 11/24] RISC-V: Update E order and I extension order, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 17/24] RISC-V: Remove braces from satp case statement, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 18/24] RISC-V: riscv-qemu port supports sv39 and sv48, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 20/24] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 19/24] RISC-V: vectored traps are optional, Michael Clark, 2018/03/21