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[Qemu-devel] [PATCH v8 32/35] RISC-V: Implement mstatus.TSR/TW/TVM
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v8 32/35] RISC-V: Implement mstatus.TSR/TW/TVM |
Date: |
Thu, 26 Apr 2018 11:45:35 +1200 |
This adds the necessary minimum to support S-mode
virtualization for priv ISA >= v1.10
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Cc: Matthew Suozzo <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Co-authored-by: Matthew Suozzo <address@hidden>
Co-authored-by: Michael Clark <address@hidden>
---
target/riscv/csr.c | 17 +++++++++++++----
target/riscv/op_helper.c | 25 +++++++++++++++++++++----
2 files changed, 34 insertions(+), 8 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index e005285..da66908 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -313,7 +313,8 @@ static int write_mstatus(CPURISCVState *env, int csrno,
target_ulong val)
}
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
- MSTATUS_MPP | MSTATUS_MXR;
+ MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
+ MSTATUS_TW;
}
/* silenty discard mstatus.mpp writes for unsupported modes */
@@ -650,7 +651,11 @@ static int read_satp(CPURISCVState *env, int csrno,
target_ulong *val)
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
*val = 0;
} else if (env->priv_ver >= PRIV_VERSION_1_10_0) {
- *val = env->satp;
+ if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
+ return -1;
+ } else {
+ *val = env->satp;
+ }
} else {
*val = env->sptbr;
}
@@ -671,8 +676,12 @@ static int write_satp(CPURISCVState *env, int csrno,
target_ulong val)
validate_vm(env, get_field(val, SATP_MODE)) &&
((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
{
- tlb_flush(CPU(riscv_env_get_cpu(env)));
- env->satp = val;
+ if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
+ return -1;
+ } else {
+ tlb_flush(CPU(riscv_env_get_cpu(env)));
+ env->satp = val;
+ }
}
return 0;
}
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index 81bd1a7..77c79ba 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -82,6 +82,11 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong
cpu_pc_deb)
do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC());
}
+ if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
+ get_field(env->mstatus, MSTATUS_TSR)) {
+ do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ }
+
target_ulong mstatus = env->mstatus;
target_ulong prev_priv = get_field(mstatus, MSTATUS_SPP);
mstatus = set_field(mstatus,
@@ -125,16 +130,28 @@ void helper_wfi(CPURISCVState *env)
{
CPUState *cs = CPU(riscv_env_get_cpu(env));
- cs->halted = 1;
- cs->exception_index = EXCP_HLT;
- cpu_loop_exit(cs);
+ if (env->priv == PRV_S &&
+ env->priv_ver >= PRIV_VERSION_1_10_0 &&
+ get_field(env->mstatus, MSTATUS_TW)) {
+ do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ } else {
+ cs->halted = 1;
+ cs->exception_index = EXCP_HLT;
+ cpu_loop_exit(cs);
+ }
}
void helper_tlb_flush(CPURISCVState *env)
{
RISCVCPU *cpu = riscv_env_get_cpu(env);
CPUState *cs = CPU(cpu);
- tlb_flush(cs);
+ if (env->priv == PRV_S &&
+ env->priv_ver >= PRIV_VERSION_1_10_0 &&
+ get_field(env->mstatus, MSTATUS_TVM)) {
+ do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+ } else {
+ tlb_flush(cs);
+ }
}
#endif /* !CONFIG_USER_ONLY */
--
2.7.0
- [Qemu-devel] [PATCH v8 23/35] RISC-V: Simplify riscv_cpu_local_irqs_pending, (continued)
- [Qemu-devel] [PATCH v8 23/35] RISC-V: Simplify riscv_cpu_local_irqs_pending, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 24/35] RISC-V: Allow setting and clearing multiple irqs, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 25/35] RISC-V: Move non-ops from op_helper to cpu_helper, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 26/35] RISC-V: Update CSR and interrupt definitions, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 28/35] RISC-V: Implement atomic mip/sip CSR updates, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 27/35] RISC-V: Implement modular CSR helper interface, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 29/35] RISC-V: Implement existential predicates for CSRs, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 30/35] RISC-V: Split out mstatus_fs from tb_flags, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 31/35] RISC-V: Mark mstatus.fs dirty, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 32/35] RISC-V: Implement mstatus.TSR/TW/TVM,
Michael Clark <=
- [Qemu-devel] [PATCH v8 33/35] RISC-V: Add public API for the CSR dispatch table, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 34/35] RISC-V: Add hartid and \n to interrupt logging, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 35/35] RISC-V: Use riscv prefix consistently on cpu helpers, Michael Clark, 2018/04/25
- Re: [Qemu-devel] [PATCH v8 00/35] QEMU 2.13 Privileged ISA emulation updates, Michael Clark, 2018/04/25