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Re: [Qemu-devel] [PATCH] RISC-V: Fix missing break statement in disassem
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From: |
Philippe Mathieu-Daudé |
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Subject: |
Re: [Qemu-devel] [PATCH] RISC-V: Fix missing break statement in disassembler |
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Date: |
Tue, 1 May 2018 19:54:38 -0300 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 |
On 04/29/2018 08:18 PM, Michael Clark wrote:
> This fixes an issue when disassembling rv128 c.sqsp,
> where the code erroneously fell through to c.swsp.
>
> Cc: Palmer Dabbelt <address@hidden>
> Cc: Sagar Karandikar <address@hidden>
> Cc: Bastian Koppelmann <address@hidden>
> Cc: Peter Maydell <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> ---
> disas/riscv.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 74ad16eacdd3..ea19f6fbe2b1 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -1470,8 +1470,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa
> isa)
> if (isa == rv128) {
> op = rv_op_c_sqsp;
> } else {
> - op = rv_op_c_fsdsp; break;
> + op = rv_op_c_fsdsp;
> }
> + break;
> case 6: op = rv_op_c_swsp; break;
> case 7:
> if (isa == rv32) {
>