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[Qemu-devel] [PULL 07/20] RISC-V: Fix missing break statement in disasse
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PULL 07/20] RISC-V: Fix missing break statement in disassembler |
Date: |
Sun, 6 May 2018 11:35:12 +1200 |
This fixes an issue when disassembling rv128 c.sqsp,
where the code erroneously fell through to c.swsp.
Cc: Palmer Dabbelt <address@hidden>
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Alistair Francis <address@hidden>
Cc: Peter Maydell <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
---
disas/riscv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 2cecf0d8558d..7fd1019623ee 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1470,8 +1470,9 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
if (isa == rv128) {
op = rv_op_c_sqsp;
} else {
- op = rv_op_c_fsdsp; break;
+ op = rv_op_c_fsdsp;
}
+ break;
case 6: op = rv_op_c_swsp; break;
case 7:
if (isa == rv32) {
--
2.7.0
- [Qemu-devel] [PULL 00/20] RISC-V: QEMU 2.13 Privileged ISA emulation updates, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 01/20] RISC-V: Replace hardcoded constants with enum values, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 02/20] RISC-V: Make virt board description match spike, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 03/20] RISC-V: Use ROM base address and size from memmap, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 04/20] RISC-V: Remove identity_translate from load_elf, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 05/20] RISC-V: Remove unused class definitions, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 06/20] RISC-V: Include instruction hex in disassembly, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 07/20] RISC-V: Fix missing break statement in disassembler,
Michael Clark <=
- [Qemu-devel] [PULL 08/20] RISC-V: Make some header guards more specific, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 09/20] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 11/20] RISC-V: Remove erroneous comment from translate.c, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 10/20] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 12/20] RISC-V: Update E and I extension order, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 13/20] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 14/20] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 15/20] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 16/20] RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 17/20] RISC-V: Add mcycle/minstret support for -icount auto, Michael Clark, 2018/05/05