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[Qemu-devel] [PULL 19/20] RISC-V: No traps on writes to misa, minstret,
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PULL 19/20] RISC-V: No traps on writes to misa, minstret, mcycle |
Date: |
Sun, 6 May 2018 11:35:24 +1200 |
These fields are marked WARL (Write Any Values, Reads
Legal Values) in the RISC-V Privileged Architecture
Specification so instead of raising exceptions,
illegal writes are silently dropped.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
---
target/riscv/op_helper.c | 25 +++++++++++++------------
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index af0c52a48418..3abf52453cfc 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -213,17 +213,19 @@ void csr_write_helper(CPURISCVState *env, target_ulong
val_to_write,
break;
}
case CSR_MINSTRET:
- qemu_log_mask(LOG_UNIMP, "CSR_MINSTRET: write not implemented");
- goto do_illegal;
+ /* minstret is WARL so unsupported writes are ignored */
+ break;
case CSR_MCYCLE:
- qemu_log_mask(LOG_UNIMP, "CSR_MCYCLE: write not implemented");
- goto do_illegal;
+ /* mcycle is WARL so unsupported writes are ignored */
+ break;
+#if defined(TARGET_RISCV32)
case CSR_MINSTRETH:
- qemu_log_mask(LOG_UNIMP, "CSR_MINSTRETH: write not implemented");
- goto do_illegal;
+ /* minstreth is WARL so unsupported writes are ignored */
+ break;
case CSR_MCYCLEH:
- qemu_log_mask(LOG_UNIMP, "CSR_MCYCLEH: write not implemented");
- goto do_illegal;
+ /* mcycleh is WARL so unsupported writes are ignored */
+ break;
+#endif
case CSR_MUCOUNTEREN:
if (env->priv_ver <= PRIV_VERSION_1_09_1) {
env->scounteren = val_to_write;
@@ -337,10 +339,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong
val_to_write,
case CSR_MBADADDR:
env->mbadaddr = val_to_write;
break;
- case CSR_MISA: {
- qemu_log_mask(LOG_UNIMP, "CSR_MISA: misa writes not supported");
- goto do_illegal;
- }
+ case CSR_MISA:
+ /* misa is WARL so unsupported writes are ignored */
+ break;
case CSR_PMPCFG0:
case CSR_PMPCFG1:
case CSR_PMPCFG2:
--
2.7.0
- [Qemu-devel] [PULL 09/20] RISC-V: Make virt header comment title consistent, (continued)
- [Qemu-devel] [PULL 09/20] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 11/20] RISC-V: Remove erroneous comment from translate.c, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 10/20] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 12/20] RISC-V: Update E and I extension order, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 13/20] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 14/20] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 15/20] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 16/20] RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 17/20] RISC-V: Add mcycle/minstret support for -icount auto, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 18/20] RISC-V: Make mtvec/stvec ignore vectored traps, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 19/20] RISC-V: No traps on writes to misa, minstret, mcycle,
Michael Clark <=
- [Qemu-devel] [PULL 20/20] RISC-V: Mark ROM read-only after copying in code, Michael Clark, 2018/05/05
- Re: [Qemu-devel] [PULL 00/20] RISC-V: QEMU 2.13 Privileged ISA emulation updates, Peter Maydell, 2018/05/08