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[Qemu-devel] [PATCH v1 1/6] target/riscv: avoid integer overflow in next
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v1 1/6] target/riscv: avoid integer overflow in next_page PC check |
Date: |
Wed, 9 May 2018 22:11:48 +1200 |
From: "Emilio G. Cota" <address@hidden>
If the PC is in the last page of the address space, next_page_start
overflows to 0. Fix it.
Reported-by: Richard Henderson <address@hidden>
Suggested-by: Richard Henderson <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Michael Clark <address@hidden>
Acked-by: Bastian Koppelmann <address@hidden>
Cc: Michael Clark <address@hidden>
Cc: Palmer Dabbelt <address@hidden>
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Emilio G. Cota <address@hidden>
---
target/riscv/translate.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c0e6a044d383..a98033ca77ca 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1850,11 +1850,11 @@ void gen_intermediate_code(CPUState *cs,
TranslationBlock *tb)
CPURISCVState *env = cs->env_ptr;
DisasContext ctx;
target_ulong pc_start;
- target_ulong next_page_start;
+ target_ulong page_start;
int num_insns;
int max_insns;
pc_start = tb->pc;
- next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
+ page_start = pc_start & TARGET_PAGE_MASK;
ctx.pc = pc_start;
/* once we have GDB, the rest of the translate.c implementation should be
@@ -1904,7 +1904,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock
*tb)
if (cs->singlestep_enabled) {
break;
}
- if (ctx.pc >= next_page_start) {
+ if (ctx.pc - page_start >= TARGET_PAGE_SIZE) {
break;
}
if (tcg_op_buf_full()) {
--
2.7.0
- [Qemu-devel] [PATCH v1 0/6] Translation loop conversion for riscv, Michael Clark, 2018/05/09
- [Qemu-devel] [PATCH v1 1/6] target/riscv: avoid integer overflow in next_page PC check,
Michael Clark <=
- [Qemu-devel] [PATCH v1 2/6] translator: merge max_insns into DisasContextBase, Michael Clark, 2018/05/09
- [Qemu-devel] [PATCH v1 3/6] target/riscv: convert to DisasJumpType, Michael Clark, 2018/05/09
- [Qemu-devel] [PATCH v1 4/6] target/riscv: convert to DisasContextBase, Michael Clark, 2018/05/09
- [Qemu-devel] [PATCH v1 5/6] target/riscv: convert to TranslatorOps, Michael Clark, 2018/05/09
- [Qemu-devel] [PATCH v1 6/6] target/riscv: add misa to DisasContext, Michael Clark, 2018/05/09