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[Qemu-devel] [PULL 09/16] target/arm: Implement FP data-processing (2 so
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 09/16] target/arm: Implement FP data-processing (2 source) for fp16 |
Date: |
Tue, 15 May 2018 15:07:00 +0100 |
From: Richard Henderson <address@hidden>
We missed all of the scalar fp16 binary operations.
Cc: address@hidden
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 65 ++++++++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 78f12daaf6..66607668ce 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -5299,6 +5299,61 @@ static void handle_fp_2src_double(DisasContext *s, int
opcode,
tcg_temp_free_i64(tcg_res);
}
+/* Floating-point data-processing (2 source) - half precision */
+static void handle_fp_2src_half(DisasContext *s, int opcode,
+ int rd, int rn, int rm)
+{
+ TCGv_i32 tcg_op1;
+ TCGv_i32 tcg_op2;
+ TCGv_i32 tcg_res;
+ TCGv_ptr fpst;
+
+ tcg_res = tcg_temp_new_i32();
+ fpst = get_fpstatus_ptr(true);
+ tcg_op1 = read_fp_hreg(s, rn);
+ tcg_op2 = read_fp_hreg(s, rm);
+
+ switch (opcode) {
+ case 0x0: /* FMUL */
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
+ break;
+ case 0x1: /* FDIV */
+ gen_helper_advsimd_divh(tcg_res, tcg_op1, tcg_op2, fpst);
+ break;
+ case 0x2: /* FADD */
+ gen_helper_advsimd_addh(tcg_res, tcg_op1, tcg_op2, fpst);
+ break;
+ case 0x3: /* FSUB */
+ gen_helper_advsimd_subh(tcg_res, tcg_op1, tcg_op2, fpst);
+ break;
+ case 0x4: /* FMAX */
+ gen_helper_advsimd_maxh(tcg_res, tcg_op1, tcg_op2, fpst);
+ break;
+ case 0x5: /* FMIN */
+ gen_helper_advsimd_minh(tcg_res, tcg_op1, tcg_op2, fpst);
+ break;
+ case 0x6: /* FMAXNM */
+ gen_helper_advsimd_maxnumh(tcg_res, tcg_op1, tcg_op2, fpst);
+ break;
+ case 0x7: /* FMINNM */
+ gen_helper_advsimd_minnumh(tcg_res, tcg_op1, tcg_op2, fpst);
+ break;
+ case 0x8: /* FNMUL */
+ gen_helper_advsimd_mulh(tcg_res, tcg_op1, tcg_op2, fpst);
+ tcg_gen_xori_i32(tcg_res, tcg_res, 0x8000);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
+ write_fp_sreg(s, rd, tcg_res);
+
+ tcg_temp_free_ptr(fpst);
+ tcg_temp_free_i32(tcg_op1);
+ tcg_temp_free_i32(tcg_op2);
+ tcg_temp_free_i32(tcg_res);
+}
+
/* Floating point data-processing (2 source)
* 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
* +---+---+---+-----------+------+---+------+--------+-----+------+------+
@@ -5331,6 +5386,16 @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
}
handle_fp_2src_double(s, opcode, rd, rn, rm);
break;
+ case 3:
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+ unallocated_encoding(s);
+ return;
+ }
+ if (!fp_access_check(s)) {
+ return;
+ }
+ handle_fp_2src_half(s, opcode, rd, rn, rm);
+ break;
default:
unallocated_encoding(s);
}
--
2.17.0
- [Qemu-devel] [PULL 00/16] target-arm queue, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 04/16] target/arm: Implement FMOV (general) for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 07/16] target/arm: Implement FCVT (scalar, fixed-point) for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 06/16] target/arm: Implement FCVT (scalar, integer) for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 03/16] target/arm: Fix fp_status_f16 tininess before rounding, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 12/16] target/arm: Implement FCSEL for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 01/16] fpu/softfloat: int_to_float ensure r fully initialised, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 11/16] target/arm: Implement FCMP for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 10/16] target/arm: Implement FP data-processing (3 source) for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 08/16] target/arm: Introduce and use read_fp_hreg, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 09/16] target/arm: Implement FP data-processing (2 source) for fp16,
Peter Maydell <=
- [Qemu-devel] [PULL 02/16] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT), Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 05/16] target/arm: Early exit after unallocated_encoding in disas_fp_int_conv, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 13/16] target/arm: Implement FMOV (immediate) for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 16/16] tcg: Optionally log FPU state in TCG -d cpu logging, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 15/16] sdcard: Correct CRC16 offset in sd_function_switch(), Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 14/16] target/arm: Fix sqrt_f16 exception raising, Peter Maydell, 2018/05/15
- Re: [Qemu-devel] [PULL 00/16] target-arm queue, Peter Maydell, 2018/05/15