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[Qemu-devel] [PATCH v1 29/30] RISC-V: Don't add NULL bootargs to device-
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v1 29/30] RISC-V: Don't add NULL bootargs to device-tree |
Date: |
Wed, 23 May 2018 12:15:16 +1200 |
---
hw/riscv/sifive_u.c | 4 +++-
hw/riscv/spike.c | 6 ++++--
hw/riscv/virt.c | 4 +++-
3 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 326b0f434cff..02721d43c474 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -206,7 +206,9 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
- qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ if (cmdline) {
+ qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ }
g_free(nodename);
}
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index f94e2b670799..5dd7d28aed4e 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -156,8 +156,10 @@ static void create_fdt(SpikeState *s, const struct
MemmapEntry *memmap,
g_free(cells);
g_free(nodename);
- qemu_fdt_add_subnode(fdt, "/chosen");
- qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ if (cmdline) {
+ qemu_fdt_add_subnode(fdt, "/chosen");
+ qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ }
}
static void spike_v1_10_0_board_init(MachineState *machine)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 321fa6e8122a..c889aa3cd269 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -253,7 +253,9 @@ static void *create_fdt(RISCVVirtState *s, const struct
MemmapEntry *memmap,
qemu_fdt_add_subnode(fdt, "/chosen");
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
- qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ if (cmdline) {
+ qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+ }
g_free(nodename);
return fdt;
--
2.7.0
- [Qemu-devel] [PATCH v1 22/30] RISC-V: Add misa runtime write support, (continued)
- [Qemu-devel] [PATCH v1 22/30] RISC-V: Add misa runtime write support, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 23/30] RISC-V: Fix CLINT timecmp low 32-bit writes, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 24/30] RISC-V: Fix PLIC pending bitfield reads, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 25/30] RISC-V: Enable second UART on sifive_e and sifive_u, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 26/30] RISC-V: Remove unnecessary disassembler constraints, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 27/30] elf: Add RISC-V PSABI ELF header defines, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 28/30] RISC-V: linux-user support for RVE ABI, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 29/30] RISC-V: Don't add NULL bootargs to device-tree,
Michael Clark <=
- [Qemu-devel] [PATCH v1 30/30] RISC-V: Support separate firmware and kernel payload, Michael Clark, 2018/05/22