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Re: [Qemu-devel] [PATCH v1 15/30] RISC-V: Add hartid and \n to interrupt
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH v1 15/30] RISC-V: Add hartid and \n to interrupt logging |
Date: |
Thu, 24 May 2018 15:47:22 -0700 |
On Wed, May 23, 2018 at 5:33 AM, Philippe Mathieu-Daudé <address@hidden> wrote:
> Hi Michael,
>
> On 05/22/2018 09:15 PM, Michael Clark wrote:
>> Add carriage return that was erroneously removed
>> when converting to qemu_log. Change hard coded
>> core number to the actual hartid.
>
> I think it makes more sens to move this patch before your 6/30 "Move
> non-ops from op_helper to cpu_helper".
>
>>
>> Cc: Sagar Karandikar <address@hidden>
>> Cc: Bastian Koppelmann <address@hidden>
>> Cc: Palmer Dabbelt <address@hidden>
>> Cc: Alistair Francis <address@hidden>
>> Signed-off-by: Michael Clark <address@hidden>
>
> Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
>
>> ---
>> target/riscv/cpu_helper.c | 18 ++++++++++--------
>> 1 file changed, 10 insertions(+), 8 deletions(-)
>>
>> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>> index bc15e19022cc..69592c037042 100644
>> --- a/target/riscv/cpu_helper.c
>> +++ b/target/riscv/cpu_helper.c
>> @@ -446,11 +446,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>> if (RISCV_DEBUG_INTERRUPT) {
>> int log_cause = cs->exception_index & RISCV_EXCP_INT_MASK;
>> if (cs->exception_index & RISCV_EXCP_INT_FLAG) {
>> - qemu_log_mask(LOG_TRACE, "core 0: trap %s, epc 0x"
>> TARGET_FMT_lx,
>> - riscv_intr_names[log_cause], env->pc);
>> + qemu_log_mask(LOG_TRACE, "core "
>> + TARGET_FMT_ld ": trap %s, epc 0x" TARGET_FMT_lx "\n",
>> + env->mhartid, riscv_intr_names[log_cause], env->pc);
>> } else {
>> - qemu_log_mask(LOG_TRACE, "core 0: intr %s, epc 0x"
>> TARGET_FMT_lx,
>> - riscv_excp_names[log_cause], env->pc);
>> + qemu_log_mask(LOG_TRACE, "core "
>> + TARGET_FMT_ld ": intr %s, epc 0x" TARGET_FMT_lx "\n",
>> + env->mhartid, riscv_excp_names[log_cause], env->pc);
>> }
>> }
>>
>> @@ -512,8 +514,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>>
>> if (hasbadaddr) {
>> if (RISCV_DEBUG_INTERRUPT) {
>> - qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld
>> - ": badaddr 0x" TARGET_FMT_lx, env->mhartid,
>> env->badaddr);
>> + qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": badaddr
>> 0x"
>> + TARGET_FMT_lx "\n", env->mhartid, env->badaddr);
>> }
>> env->sbadaddr = env->badaddr;
>> } else {
>> @@ -537,8 +539,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>>
>> if (hasbadaddr) {
>> if (RISCV_DEBUG_INTERRUPT) {
>> - qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld
>> - ": badaddr 0x" TARGET_FMT_lx, env->mhartid,
>> env->badaddr);
>> + qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": badaddr
>> 0x"
>> + TARGET_FMT_lx "\n", env->mhartid, env->badaddr);
>> }
>> env->mbadaddr = env->badaddr;
>> } else {
>>
>
- [Qemu-devel] [PATCH v1 11/30] RISC-V: Split out mstatus_fs from tb_flags, (continued)
- [Qemu-devel] [PATCH v1 11/30] RISC-V: Split out mstatus_fs from tb_flags, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 12/30] RISC-V: Mark mstatus.fs dirty, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 13/30] RISC-V: Implement mstatus.TSR/TW/TVM, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 14/30] RISC-V: Add public API for the CSR dispatch table, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 15/30] RISC-V: Add hartid and \n to interrupt logging, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 16/30] RISC-V: Use riscv prefix consistently on cpu helpers, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 17/30] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 18/30] RISC-V: Add missing free for plic_hart_config, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 19/30] RISC-V: Allow interrupt controllers to claim interrupts, Michael Clark, 2018/05/22