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[Qemu-devel] [PULL v1 19/38] target-microblaze: dec_msr: Fix MTS to FSR
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PULL v1 19/38] target-microblaze: dec_msr: Fix MTS to FSR |
Date: |
Tue, 29 May 2018 12:49:52 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Fix moves to FSR. Not only bit 31 is accessible.
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/translate.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 6a270fbece..6f2cafa88a 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -533,11 +533,9 @@ static void dec_msr(DisasContext *dc)
break;
case SR_EAR:
case SR_ESR:
+ case SR_FSR:
tcg_gen_mov_i32(cpu_SR[sr], cpu_R[dc->ra]);
break;
- case 0x7:
- tcg_gen_andi_i32(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
- break;
case 0x800:
tcg_gen_st_i32(cpu_R[dc->ra],
cpu_env, offsetof(CPUMBState, slr));
--
2.14.1
- [Qemu-devel] [PULL v1 09/38] target-microblaze: Conditionalize setting of PVR11_USE_MMU, (continued)
- [Qemu-devel] [PULL v1 09/38] target-microblaze: Conditionalize setting of PVR11_USE_MMU, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 08/38] target-microblaze: Remove USE_MMU PVR checks, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 10/38] target-microblaze: Bypass MMU with MMU_NOMMU_IDX, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 11/38] target-microblaze: Make compute_ldst_addr always use a temp, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 12/38] target-microblaze: Remove pointer indirection for ld/st addresses, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 07/38] target-microblaze: Tighten up TCGv_i32 vs TCGv type usage, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 14/38] target-microblaze: Name special registers we support, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 13/38] target-microblaze: Use TCGv for load/store addresses, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 17/38] target-microblaze: dec_msr: Use bool and extract32, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 15/38] target-microblaze: Break out trap_userspace(), Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 19/38] target-microblaze: dec_msr: Fix MTS to FSR,
Edgar E. Iglesias <=
- [Qemu-devel] [PULL v1 16/38] target-microblaze: Break out trap_illegal(), Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 18/38] target-microblaze: dec_msr: Reuse more code when reg-decoding, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 21/38] target-microblaze: Setup for 64bit addressing, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 23/38] target-microblaze: Implement MFSE EAR, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 20/38] target-microblaze: Make special registers 64-bit, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 24/38] target-microblaze: mmu: Add R_TBLX_MISS macros, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 26/38] target-microblaze: mmu: Prepare for 64-bit addresses, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 25/38] target-microblaze: mmu: Remove unused register state, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 27/38] target-microblaze: mmu: Add a configurable output address mask, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 28/38] target-microblaze: dec_msr: Plug a temp leak, Edgar E. Iglesias, 2018/05/29