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[Qemu-devel] [PULL v1 36/38] target-microblaze: Use tcg_gen_movcond in e
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PULL v1 36/38] target-microblaze: Use tcg_gen_movcond in eval_cond_jmp |
Date: |
Tue, 29 May 2018 12:50:09 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
Cleanup eval_cond_jmp to use tcg_gen_movcond_i64().
No functional change.
Suggested-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target/microblaze/translate.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 591d232304..b79600cba5 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1171,12 +1171,16 @@ static inline void eval_cc(DisasContext *dc, unsigned
int cc,
static void eval_cond_jmp(DisasContext *dc, TCGv_i64 pc_true, TCGv_i64
pc_false)
{
- TCGLabel *l1 = gen_new_label();
- /* Conditional jmp. */
- tcg_gen_mov_i64(cpu_SR[SR_PC], pc_false);
- tcg_gen_brcondi_i32(TCG_COND_EQ, env_btaken, 0, l1);
- tcg_gen_mov_i64(cpu_SR[SR_PC], pc_true);
- gen_set_label(l1);
+ TCGv_i64 tmp_btaken = tcg_temp_new_i64();
+ TCGv_i64 tmp_zero = tcg_const_i64(0);
+
+ tcg_gen_extu_i32_i64(tmp_btaken, env_btaken);
+ tcg_gen_movcond_i64(TCG_COND_NE, cpu_SR[SR_PC],
+ tmp_btaken, tmp_zero,
+ pc_true, pc_false);
+
+ tcg_temp_free_i64(tmp_btaken);
+ tcg_temp_free_i64(tmp_zero);
}
static void dec_bcc(DisasContext *dc)
--
2.14.1
- [Qemu-devel] [PULL v1 24/38] target-microblaze: mmu: Add R_TBLX_MISS macros, (continued)
- [Qemu-devel] [PULL v1 24/38] target-microblaze: mmu: Add R_TBLX_MISS macros, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 26/38] target-microblaze: mmu: Prepare for 64-bit addresses, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 25/38] target-microblaze: mmu: Remove unused register state, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 27/38] target-microblaze: mmu: Add a configurable output address mask, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 28/38] target-microblaze: dec_msr: Plug a temp leak, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 30/38] target-microblaze: Allow address sizes between 32 and 64 bits, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 29/38] target-microblaze: Add support for extended access to TLBLO, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 31/38] target-microblaze: Simplify address computation using tcg_gen_addi_i32(), Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 32/38] target-microblaze: mmu: Cleanup debug log messages, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 33/38] target-microblaze: Use table based condition-codes conversion, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 36/38] target-microblaze: Use tcg_gen_movcond in eval_cond_jmp,
Edgar E. Iglesias <=
- [Qemu-devel] [PULL v1 34/38] target-microblaze: Remove argument b in eval_cc(), Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 35/38] target-microblaze: Convert env_btarget to i64, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 37/38] target-microblaze: cpu_mmu_index: Fixup indentation, Edgar E. Iglesias, 2018/05/29
- [Qemu-devel] [PULL v1 38/38] target-microblaze: Consolidate MMU enabled checks, Edgar E. Iglesias, 2018/05/29
- Re: [Qemu-devel] [PULL v1 00/38] Xilinx queue, Peter Maydell, 2018/05/29