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Re: [Qemu-devel] [PATCH v2 05/13] hw/misc/tz-mpc.c: Implement the Arm Tr
From: |
Auger Eric |
Subject: |
Re: [Qemu-devel] [PATCH v2 05/13] hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller |
Date: |
Fri, 15 Jun 2018 15:23:08 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.4.0 |
Hi Peter,
On 06/15/2018 10:53 AM, Peter Maydell wrote:
> On 15 June 2018 at 08:10, Auger Eric <address@hidden> wrote:
>> after reading 8/13, I have a doubt here about the ret.perm value that
>> stays IOMMU_RW independently on the translation success. Usually if the
>> translation failn perm is set to IOMMU_NONE. In your case you also play
>> with the output address space which switches to the blocked one in case
>> of failure and you handle access failure through that means. So maybe
>> the end result is the same but I am not sure.
>
> The end result is different, which is why we have to return RW here.
> If we return NONE we are telling the caller that this will be
> a memory transaction failure, so the CPU emulation will generate
> a bus-error kind of exception. By returning RW we tell the caller
> that it should make transactions for this address. We can then
> handle them in the MPC with the correct behaviour for a blocked
> access (generating an interrupt, and configurably either completing
> the access as RAZ/WI or returning MEMTX_ERROR to cause a busfault.)
OK thank you for the explanation
Eric
>
> thanks
> -- PMM
>
- [Qemu-devel] [PATCH v2 08/13] hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate, (continued)
- [Qemu-devel] [PATCH v2 08/13] hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate, Peter Maydell, 2018/06/04
- [Qemu-devel] [PATCH v2 10/13] hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS, Peter Maydell, 2018/06/04
- [Qemu-devel] [PATCH v2 03/13] iommu: Add IOMMU index argument to translate method, Peter Maydell, 2018/06/04
- [Qemu-devel] [PATCH v2 01/13] iommu: Add IOMMU index concept to IOMMU API, Peter Maydell, 2018/06/04
- [Qemu-devel] [PATCH v2 05/13] hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller, Peter Maydell, 2018/06/04
- [Qemu-devel] [PATCH v2 06/13] hw/misc/tz-mpc.c: Implement registers, Peter Maydell, 2018/06/04
- Re: [Qemu-devel] [PATCH v2 06/13] hw/misc/tz-mpc.c: Implement registers, Auger Eric, 2018/06/15
[Qemu-devel] [PATCH v2 02/13] iommu: Add IOMMU index argument to notifier APIs, Peter Maydell, 2018/06/04