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[Qemu-devel] [PULL 13/43] cpu-defs.h: Document CPUIOTLBEntry 'addr' fiel
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 13/43] cpu-defs.h: Document CPUIOTLBEntry 'addr' field |
Date: |
Fri, 15 Jun 2018 15:24:51 +0100 |
The 'addr' field in the CPUIOTLBEntry struct has a rather non-obvious
use; add a comment documenting it (reverse-engineered from what
the code that sets it is doing).
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Paolo Bonzini <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
include/exec/cpu-defs.h | 9 +++++++++
accel/tcg/cputlb.c | 12 ++++++++++++
2 files changed, 21 insertions(+)
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index e43ff8346b1..a171ffc1a45 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -127,6 +127,15 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 <<
CPU_TLB_ENTRY_BITS));
* structs into one.)
*/
typedef struct CPUIOTLBEntry {
+ /*
+ * @addr contains:
+ * - in the lower TARGET_PAGE_BITS, a physical section number
+ * - with the lower TARGET_PAGE_BITS masked off, an offset which
+ * must be added to the virtual address to obtain:
+ * + the ram_addr_t of the target RAM (if the physical section
+ * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM)
+ * + the offset within the target MemoryRegion (otherwise)
+ */
hwaddr addr;
MemTxAttrs attrs;
} CPUIOTLBEntry;
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 05439039e91..31f7695cb29 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -664,6 +664,18 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong
vaddr,
env->iotlb_v[mmu_idx][vidx] = env->iotlb[mmu_idx][index];
/* refill the tlb */
+ /*
+ * At this point iotlb contains a physical section number in the lower
+ * TARGET_PAGE_BITS, and either
+ * + the ram_addr_t of the page base of the target RAM (if NOTDIRTY or
ROM)
+ * + the offset within section->mr of the page base (otherwise)
+ * We subtract the vaddr (which is page aligned and thus won't
+ * disturb the low bits) to give an offset which can be added to the
+ * (non-page-aligned) vaddr of the eventual memory access to get
+ * the MemoryRegion offset for the access. Note that the vaddr we
+ * subtract here is that of the page base, and not the same as the
+ * vaddr we add back in io_readx()/io_writex()/get_page_addr_code().
+ */
env->iotlb[mmu_idx][index].addr = iotlb - vaddr;
env->iotlb[mmu_idx][index].attrs = attrs;
--
2.17.1
- [Qemu-devel] [PULL 00/43] target-arm queue, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 10/43] hw/arm/armv7m: Remove unused armv7m_init() function, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 11/43] arm: Don't crash if user tries to use a Cortex-M CPU without an NVIC, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 13/43] cpu-defs.h: Document CPUIOTLBEntry 'addr' field,
Peter Maydell <=
- [Qemu-devel] [PULL 08/43] hw/char/parallel: Convert away from old_mmio, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 07/43] hw/input/pckbd: Convert away from old_mmio, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 05/43] hw/block/pflash_cfi02: Convert away from old_mmio, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 17/43] exec.c: Don't accidentally sign-extend 4-byte loads in subpage_read(), Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 16/43] bswap: Add new stn_*_p() and ldn_*_p() memory access functions, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 04/43] hw/m68k/mcf5206: Convert away from old_mmio, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 15/43] CODING_STYLE: Define our preferred form for multiline comments, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 09/43] stellaris: Stop using armv7m_init(), Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 23/43] target/arm: Implement SVE compress active elements, Peter Maydell, 2018/06/15
- [Qemu-devel] [PULL 06/43] hw/watchdog/wdt_i6300esb: Convert away from old_mmio, Peter Maydell, 2018/06/15