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[Qemu-devel] [PULL 26/28] target/arm: Strict alignment for ARMv6-M and A
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 26/28] target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline |
Date: |
Fri, 22 Jun 2018 13:57:11 +0100 |
From: Julia Suvorova <address@hidden>
Unlike ARMv7-M, ARMv6-M and ARMv8-M Baseline only supports naturally
aligned memory accesses for load/store instructions.
Signed-off-by: Julia Suvorova <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index b988d379e7c..2a3e4f5d4c9 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1100,7 +1100,14 @@ static inline TCGv gen_aa32_addr(DisasContext *s,
TCGv_i32 a32, TCGMemOp op)
static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
int index, TCGMemOp opc)
{
- TCGv addr = gen_aa32_addr(s, a32, opc);
+ TCGv addr;
+
+ if (arm_dc_feature(s, ARM_FEATURE_M) &&
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) {
+ opc |= MO_ALIGN;
+ }
+
+ addr = gen_aa32_addr(s, a32, opc);
tcg_gen_qemu_ld_i32(val, addr, index, opc);
tcg_temp_free(addr);
}
@@ -1108,7 +1115,14 @@ static void gen_aa32_ld_i32(DisasContext *s, TCGv_i32
val, TCGv_i32 a32,
static void gen_aa32_st_i32(DisasContext *s, TCGv_i32 val, TCGv_i32 a32,
int index, TCGMemOp opc)
{
- TCGv addr = gen_aa32_addr(s, a32, opc);
+ TCGv addr;
+
+ if (arm_dc_feature(s, ARM_FEATURE_M) &&
+ !arm_dc_feature(s, ARM_FEATURE_M_MAIN)) {
+ opc |= MO_ALIGN;
+ }
+
+ addr = gen_aa32_addr(s, a32, opc);
tcg_gen_qemu_st_i32(val, addr, index, opc);
tcg_temp_free(addr);
}
--
2.17.1
- [Qemu-devel] [PULL 16/28] xlnx-zynqmp: Swap Cortex-R5 for Cortex-R5F, (continued)
- [Qemu-devel] [PULL 16/28] xlnx-zynqmp: Swap Cortex-R5 for Cortex-R5F, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 03/28] target-arm: fix a segmentation fault due to illegal memory access, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 06/28] hw/intc/arm_gicv3: Introduce redist-region-count array property, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 19/28] hw/misc/tz-mpc.c: Implement correct blocked-access behaviour, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 02/28] target/arm: Minor cleanup for ARMv6-M 32-bit instructions, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 01/28] hw/intc/arm_gicv3: fix an extra left-shift when reading IPRIORITYR, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 21/28] hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 17/28] hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 22/28] hw/arm/iotkit: Instantiate MPC, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 23/28] hw/arm/iotkit: Wire up MPC interrupt lines, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 26/28] target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline,
Peter Maydell <=
- [Qemu-devel] [PULL 27/28] vl.c: Don't zero-initialize statics for serial_hds, Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 28/28] xen: Don't use memory_region_init_ram_nomigrate() in pci_assign_dev_load_option_rom(), Peter Maydell, 2018/06/22
- [Qemu-devel] [PULL 24/28] hw/arm/mps2-tz.c: Instantiate MPCs, Peter Maydell, 2018/06/22
- Re: [Qemu-devel] [PULL 00/28] target-arm queue, Peter Maydell, 2018/06/22