Hi,
On Tue, Aug 15, 2017 at 12:00:51PM -0500, Brijesh Singh wrote:
Add a new base CPU model called 'EPYC' to model processors from AMD EPYC
family (which includes EPYC 76xx,75xx,74xx, 73xx and 72xx).
The following features bits have been added/removed compare to Opteron_G5
Added: monitor, movbe, rdrand, mmxext, ffxsr, rdtscp, cr8legacy, osvw,
fsgsbase, bmi1, avx2, smep, bmi2, rdseed, adx, smap, clfshopt, sha
xsaveopt, xsavec, xgetbv1, arat
Removed: xop, fma4, tbm
[...]
+ {
+ .name = "EPYC",
+ .level = 0xd,
+ .vendor = CPUID_VENDOR_AMD,
+ .family = 23,
+ .model = 1,
+ .stepping = 2,
These f/m/s values trigger model-specific code in Windows 10
guests[1], and I couldn't find any public information that allow
us to fix the problem.
> Windows 10 tries to set bit 15 of MSRC001_102C, in code that
looks like workarounds for CPU Erratas.
I found a Revision Guide for family 17h[2], but it has no mention
of MSRC001_102C at all.
Can AMD help us fix this?