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Re: [Qemu-devel] [PATCH v2 1/5] i386: Add support for IA32_PRED_CMD and
From: |
Eduardo Habkost |
Subject: |
Re: [Qemu-devel] [PATCH v2 1/5] i386: Add support for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES MSRs |
Date: |
Wed, 27 Jun 2018 14:03:04 -0300 |
User-agent: |
Mutt/1.9.2 (2017-12-15) |
On Wed, Jun 27, 2018 at 07:27:20PM +0800, Robert Hoo wrote:
> IA32_PRED_CMD MSR gives software a way to issue commands that affect the state
> of indirect branch predictors. Enumerated by CPUID.(EAX=7H,ECX=0):EDX[26].
> IA32_ARCH_CAPABILITIES MSR enumerates architectural features of RDCL_NO and
> IBRS_ALL. Enumerated by CPUID.(EAX=07H, ECX=0):EDX[29].
>
> https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf
>
> Signed-off-by: Robert Hoo <address@hidden>
> ---
> target/i386/cpu.h | 4 ++++
> target/i386/kvm.c | 27 ++++++++++++++++++++++++++-
> 2 files changed, 30 insertions(+), 1 deletion(-)
>
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 89c82be..734a73e 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -352,6 +352,8 @@ typedef enum X86Seg {
> #define MSR_TSC_ADJUST 0x0000003b
> #define MSR_IA32_SPEC_CTRL 0x48
> #define MSR_VIRT_SSBD 0xc001011f
> +#define MSR_IA32_PRED_CMD 0x49
> +#define MSR_IA32_ARCH_CAPABILITIES 0x10a
> #define MSR_IA32_TSCDEADLINE 0x6e0
>
> #define FEATURE_CONTROL_LOCKED (1<<0)
> @@ -1210,6 +1212,8 @@ typedef struct CPUX86State {
>
> uint64_t spec_ctrl;
> uint64_t virt_ssbd;
> + uint64_t pred_cmd;
> + uint64_t arch_capabilities;
What's the purpose of those CPUX86State fields, if the migration
sections were removed in v2?
--
Eduardo