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Re: [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index
From: |
Stafford Horne |
Subject: |
Re: [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index |
Date: |
Thu, 28 Jun 2018 08:08:10 +0900 |
User-agent: |
Mutt/1.9.5 (2018-04-13) |
On Wed, Jun 27, 2018 at 06:50:18AM -0700, Richard Henderson wrote:
> On 06/27/2018 05:59 AM, Stafford Horne wrote:
> > The index is negative... this patch should fix that.
> >
> > @@ -78,6 +78,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong
> > spr,
> > target_ulong rb)
> > case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
> > idx = (spr - 1024);
> > env->shadow_gpr[idx / 32][idx % 32] = rb;
> > + break;
> >
> > case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR
> > 0-127 */
>
> OMG. That's embarrasing...
Yes, I thought so too, it's my bug. I am little surprised it didn't cause
issues before.
I am still getting failures on SMP, this time the kernel is jumping to some
unknown address, maybe an itlb issue, I will continue to debug. Bisecting it is
exposing some other issues (the mmu handlers were not getting init'd during one
point in time).
-Stafford
- [Qemu-devel] [PATCH v2 07/22] target/openrisc: Form the spr index from tcg, (continued)
- [Qemu-devel] [PATCH v2 07/22] target/openrisc: Form the spr index from tcg, Richard Henderson, 2018/06/18
- [Qemu-devel] [PATCH v2 08/22] target/openrisc: Merge tlb allocation into CPUOpenRISCState, Richard Henderson, 2018/06/18
- [Qemu-devel] [PATCH v2 09/22] target/openrisc: Remove indirect function calls for mmu, Richard Henderson, 2018/06/18
- [Qemu-devel] [PATCH v2 10/22] target/openrisc: Merge mmu_helper.c into mmu.c, Richard Henderson, 2018/06/18
- [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index, Richard Henderson, 2018/06/18
- Re: [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index, Stafford Horne, 2018/06/23
- Re: [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index, Stafford Horne, 2018/06/26
- Re: [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index, Richard Henderson, 2018/06/26
- Re: [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index, Stafford Horne, 2018/06/27
- Re: [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index, Richard Henderson, 2018/06/27
- Re: [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index,
Stafford Horne <=
- Re: [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index, Richard Henderson, 2018/06/27
- Re: [Qemu-devel] [PATCH v2 13/22] target/openrisc: Fix cpu_mmu_index, Stafford Horne, 2018/06/28
[Qemu-devel] [PATCH v2 12/22] target/openrisc: Fix tlb flushing in mtspr, Richard Henderson, 2018/06/18
[Qemu-devel] [PATCH v2 17/22] target/openrisc: Increase the TLB size, Richard Henderson, 2018/06/18
[Qemu-devel] [PATCH v2 16/22] target/openrisc: Log interrupts, Richard Henderson, 2018/06/18
[Qemu-devel] [PATCH v2 11/22] target/openrisc: Reduce tlb to a single dimension, Richard Henderson, 2018/06/18
[Qemu-devel] [PATCH v2 14/22] target/openrisc: Use identical sizes for ITLB and DTLB, Richard Henderson, 2018/06/18
[Qemu-devel] [PATCH v2 15/22] target/openrisc: Stub out handle_mmu_fault for softmmu, Richard Henderson, 2018/06/18