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[Qemu-devel] [PULL 33/55] target/arm: Implement SVE MOVPRFX
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 33/55] target/arm: Implement SVE MOVPRFX |
Date: |
Fri, 29 Jun 2018 15:53:25 +0100 |
From: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-sve.c | 60 +++++++++++++++++++++++++++++++++++++-
target/arm/sve.decode | 7 +++++
2 files changed, 66 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index b11b6326b94..812823777ad 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -351,6 +351,23 @@ static bool do_zpzz_ool(DisasContext *s, arg_rprr_esz *a,
gen_helper_gvec_4 *fn)
return true;
}
+/* Select active elememnts from Zn and inactive elements from Zm,
+ * storing the result in Zd.
+ */
+static void do_sel_z(DisasContext *s, int rd, int rn, int rm, int pg, int esz)
+{
+ static gen_helper_gvec_4 * const fns[4] = {
+ gen_helper_sve_sel_zpzz_b, gen_helper_sve_sel_zpzz_h,
+ gen_helper_sve_sel_zpzz_s, gen_helper_sve_sel_zpzz_d
+ };
+ unsigned vsz = vec_full_reg_size(s);
+ tcg_gen_gvec_4_ool(vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ vec_full_reg_offset(s, rm),
+ pred_full_reg_offset(s, pg),
+ vsz, vsz, 0, fns[esz]);
+}
+
#define DO_ZPZZ(NAME, name) \
static bool trans_##NAME##_zpzz(DisasContext *s, arg_rprr_esz *a, \
uint32_t insn) \
@@ -401,7 +418,13 @@ static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz
*a, uint32_t insn)
return do_zpzz_ool(s, a, fns[a->esz]);
}
-DO_ZPZZ(SEL, sel)
+static bool trans_SEL_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
+{
+ if (sve_access_check(s)) {
+ do_sel_z(s, a->rd, a->rn, a->rm, a->pg, a->esz);
+ }
+ return true;
+}
#undef DO_ZPZZ
@@ -5035,3 +5058,38 @@ static bool trans_PRF_rr(DisasContext *s, arg_PRF_rr *a,
uint32_t insn)
sve_access_check(s);
return true;
}
+
+/*
+ * Move Prefix
+ *
+ * TODO: The implementation so far could handle predicated merging movprfx.
+ * The helper functions as written take an extra source register to
+ * use in the operation, but the result is only written when predication
+ * succeeds. For unpredicated movprfx, we need to rearrange the helpers
+ * to allow the final write back to the destination to be unconditional.
+ * For predicated zeroing movprfx, we need to rearrange the helpers to
+ * allow the final write back to zero inactives.
+ *
+ * In the meantime, just emit the moves.
+ */
+
+static bool trans_MOVPRFX(DisasContext *s, arg_MOVPRFX *a, uint32_t insn)
+{
+ return do_mov_z(s, a->rd, a->rn);
+}
+
+static bool trans_MOVPRFX_m(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+{
+ if (sve_access_check(s)) {
+ do_sel_z(s, a->rd, a->rn, a->rd, a->pg, a->esz);
+ }
+ return true;
+}
+
+static bool trans_MOVPRFX_z(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
+{
+ if (sve_access_check(s)) {
+ do_movz_zpz(s, a->rd, a->rn, a->pg, a->esz);
+ }
+ return true;
+}
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 2aca9f0bb04..c725ee25843 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -270,6 +270,10 @@ ORV 00000100 .. 011 000 001 ... ..... .....
@rd_pg_rn
EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn
ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn
+# SVE constructive prefix (predicated)
+MOVPRFX_z 00000100 .. 010 000 001 ... ..... ..... @rd_pg_rn
+MOVPRFX_m 00000100 .. 010 001 001 ... ..... ..... @rd_pg_rn
+
# SVE integer add reduction (predicated)
# Note that saddv requires size != 3.
UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn
@@ -418,6 +422,9 @@ ADR_p64 00000100 11 1 ..... 1010 .. ..... .....
@rd_rn_msz_rm
### SVE Integer Misc - Unpredicated Group
+# SVE constructive prefix (unpredicated)
+MOVPRFX 00000100 00 1 00000 101111 rn:5 rd:5
+
# SVE floating-point exponential accelerator
# Note esz != 0
FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn
--
2.17.1
- [Qemu-devel] [PULL 32/55] target/arm: Implement SVE floating-point unary operations, (continued)
- [Qemu-devel] [PULL 32/55] target/arm: Implement SVE floating-point unary operations, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 15/55] target/arm: Implement SVE load and broadcast element, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 18/55] target/arm: Implement SVE prefetches, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 17/55] target/arm: Implement SVE scatter stores, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 20/55] target/arm: Implement SVE first-fault gather loads, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 22/55] target/arm: Implement SVE floating-point compare vectors, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 23/55] target/arm: Implement SVE floating-point arithmetic with immediate, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 25/55] target/arm: Implement SVE FP Fast Reduction Group, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 30/55] target/arm: Implement SVE floating-point convert to integer, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 27/55] target/arm: Implement SVE FP Compare with Zero Group, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 33/55] target/arm: Implement SVE MOVPRFX,
Peter Maydell <=
- [Qemu-devel] [PULL 37/55] target/arm: Implement SVE fp complex multiply add (indexed), Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 19/55] target/arm: Implement SVE gather loads, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 24/55] target/arm: Implement SVE Floating Point Multiply Indexed Group, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 39/55] target/arm: Implement SVE dot product (indexed), Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 12/55] target/arm: Implement SVE floating-point arithmetic (predicated), Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 29/55] target/arm: Implement SVE floating-point convert precision, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 36/55] target/arm: Pass index to AdvSIMD FCMLA (indexed), Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 13/55] target/arm: Implement SVE FP Multiply-Add Group, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 28/55] target/arm: Implement SVE floating-point trig multiply-add coefficient, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 35/55] target/arm: Implement SVE fp complex multiply add, Peter Maydell, 2018/06/29