Re: [Qemu-devel] [PATCH 6/6] target/arm: Set ISAR bits for -cpu max

[Peter Maydell]

On 29 June 2018 at 15:54, Richard Henderson
<address@hidden> wrote:
> On 06/29/2018 01:42 AM, Peter Maydell wrote:
>> On 29 June 2018 at 01:15, Richard Henderson
>> <address@hidden> wrote:
>>> For the supported extensions, fill in the appropriate bits in
>>> ID_ISAR5, ID_ISAR6, ID_AA64ISAR0, ID_AA64ISAR1.

>> This makes sense, but I'd rather have a bit of time to think
>> about how exactly we want to handle feature bits vs ID
>> register values (the current codebase is not entirely
>> coherent on the topic), so I'd rather not put this in
>> for softfreeze unless there's a strong reason we should...
>
> Fair.
>
> I was wondering if we'd post-process the feature bits to initialize the id
> registers, so that we don't have different places with the same knowledge.
>
> The clearing of EL3 bits from id_pfr1 is an example of that already.

Yes, exactly. We have a few bits that are odd like that,
where we've kind of ad-hoc tweaked stuff to make things work.
I'd rather we decided on a coherent design and then moved
the code to do that. (Another example is Aaron's PMUv3
patchset, which wants to tweak the PMU related ID registers
to match what the emulation code implements.)

The original QEMU design I think was more or less "we report
fixed ID regs which don't necessarily match our actual
capabilities" (which is also how a KVM vCPU will behave).
"Feature bits are the primary source of truth" is also a
coherent design, just not the one we started with...

thanks
-- PMM